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| page mode dual work flash memory 32m-bit, 64m-bit, 128m-bit lh28f320bf, lh28f640bf, LH28F128BF series appendix fum00701 appendix no. jan. 8, 2003 issue: rev. f
fum00701 ? handle this appendix carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products covered herein to a sales representative of the company. rev. 2.44 fum00701 1 rev. 2.44 contents page 1 introduction.............................................................. 2 1.1 features ............................................................. 2 1.2 definition of block, plane and partition........... 2 1.3 product overview ............................................. 2 1.4 product description........................................... 7 1.4.1 memory block organization ..................... 7 1.4.2 four physical planes .................................. 7 1.4.3 partition ...................................................... 7 1.4.4 parameter block ......................................... 7 1.4.5 main block................................................. 7 1.4.6 otp (one time program) block................ 7 2 principles of operation .......................................... 13 2.1 operation mode after power-up or reset mode ............................................. 13 2.2 read, program and erase operation ............... 13 2.3 status register for each partition ................... 13 2.4 data protection................................................ 13 3 bus operation ........................................................ 14 3.1 read array ...................................................... 14 3.2 output disable ................................................ 14 3.3 standby............................................................ 14 3.4 reset................................................................ 14 3.5 read identifier codes/otp............................. 15 3.6 read query ..................................................... 15 3.7 write the command to the cui ...................... 16 4 command definitions ............................................ 17 4.1 how to write the command ........................... 17 4.1.1 using dual work operation .................... 17 4.1.2 not using dual work operation ............. 18 4.1.3 full chip erase and otp program .......... 18 4.2 read array command .................................... 18 4.3 read identifier codes/otp command ........... 18 4.4 read query command.................................... 23 4.5 read status register command...................... 23 4.6 clear status register command ..................... 23 4.7 block erase command.................................... 26 4.8 full chip erase command.............................. 26 4.9 program command ......................................... 31 4.10 page buffer program command ................... 31 page 4.11 block erase suspend command and block erase resume command .................. 37 4.12 (page buffer) program suspend command and (page buffer) program resume command. 39 4.13 set block lock bit command ...................... 41 4.14 clear block lock bit command................... 44 4.15 set block lock-down bit command ........... 44 4.16 otp program command............................... 46 4.17 set partition configuration register command ...................................... 49 4.17.1 how to set the partition configuration register ...................... 49 4.17.2 partition configuration .......................... 50 5 design considerations ........................................... 53 5.1 hardware design considerations.................... 53 5.1.1 control using rst#, ce# and oe# ......... 53 5.1.2 power supply decoupling ....................... 53 5.1.3 v pp traces on printed circuit boards...... 53 5.1.4 v cc , v pp , rst# transitions.................... 53 5.1.5 power-up/down protection..................... 54 5.1.6 power dissipation .................................... 54 5.1.7 automatic power savings........................ 54 5.1.8 reset operation........................................ 54 5.2 software design considerations..................... 55 5.2.1 wsm (write state machine) polling....... 55 5.2.2 attention to program operation............... 55 5.3 data protection method .................................. 55 5.4 high performance read mode........................ 56 5.4.1 cpu compatibility................................... 56 5.4.2 using asynchronous page mode............. 56 5.4.3 single read mode.................................... 56 6 common flash interface........................................ 60 6.1 query structure output................................... 60 6.2 query structure overview .............................. 61 6.3 block status register ...................................... 61 6.4 cfi query identification string ...................... 62 6.5 system interface information.......................... 63 6.6 device geometry definition........................... 64 6.7 sharp-specific extended query table............ 66 7 related document information.............................. 80 fum00701 2 1 introduction this appendix describes how to use the lh28f320bf series, lh28f640bf series and LH28F128BF series, page mode dual work flash memory. in this document, all the functions for the lh28f320bf series, lh28f640bf series and LH28F128BF series are explained. however, the function which is available varies according to each product. refer to the specifications whether each function in this document is available or not. the function which is not described in the specifications can not be used for that product. the lh28f320bf series, lh28f640bf series and LH28F128BF series flash memory are called the product in this document. section 1 outlines the product. sections 2, 3, 4 and 5 describe the memory organization and functionality. when designing a specific system, take into design considerations described in section 5. 1.1 features the product has the following features: ? dual work operation flexible partition configuration high performance asynchronous reads page buffer program individual block locking and all blocks locked on power-up 8-word otp (one time program) block low power consumption parameter block architecture 1.2 definition of block, plane and partition block, plane and partition are defined and used in this document as explained below. refer to the specifications for the number of blocks, planes and partitions of the product which has two or more be# (ce#) pins or which has 32-bit i/o interface. block main block: 32k words. parameter block: 4k words. 32m-bit device has 8 parameter blocks and 63 main blocks. 64m-bit device has 8 parameter blocks and 127 main blocks. plane: 32m-bit and 64m-bit devices are divided into four physical planes (see table 1). plane0 or plane3 contains parameter blocks and main blocks. plane1 and plane2 consist of only main blocks. partition: read operation can be done in one partition while program/erase operation is being done in another partition. partition contains at least one plane or up to four planes. partition boundaries can be flexibly set to any plane boundary by the set partition configuration register command. if the partition configuration register is set to "111" (4 plane dual work mode), the partition is exactly the same as a plane. see section 4.17 for more information. table 1. address range of each plane (1), (2) note: 1. this table shows the density of memory area selected by each be# (ce#) when the product has two or more be# (ce#) pins 2. refer to the specifications for the address range of the product which has 32-bit i/o interface. 1.3 product overview the product is capable of dual work operation: erase or program operation on one partition and read operation on other partitions (see table 2). the partition to be accessed is automatically identified according to the input address. dual work operations can be achieved by dividing the memory array into four physical planes as shown in figure 2.1 through figure 3.2. each plane is exactly one quarter of the entire memory array. the device has also virtual partitions. several planes can be flexibly merged to one partition by writing the set partition configuration register command. this feature allows the user to read from one partition even though one of the other partitions is executing an erase or program operation. if the device is set to the 4 partitions configuration, each partition is exactly the same as each physical plane. after power-up or device reset, plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. plane # contains the blocks within the following address 32m bit 64m bit plane 0 000000h-07ffffh 000000h-0fffffh plane 1 080000h-0fffffh 100000h-1fffffh plane 2 100000h-17ffffh 200000h-2fffffh plane 3 180000h-1fffffh 300000h-3fffffh rev. 2.44 fum00701 3 during dual work operation, read operations to the partition being erased or programmed access the status register which indicates whether the erase or program operation is successfully completed or not. dual work operation cannot be executed during full chip erase and otp program mode. memory array data can be read in asynchronous 8-word page mode. the default after power-up or device reset is the asynchronous read mode in which 8-word page mode is available. the product contains a page buffer of 16 words. in the page buffer program mode, the data to be programmed is first stored into the page buffer before being transferred to the memory array. a page buffer program has high speed program performance. the page buffer program operation programs up to 16-word data at sequential addresses within one block. that is, this operation cannot be used to program data at addresses separated by something even in the same block, or divided into different blocks. page buffer program cannot be applied to otp block described later in this section. for the parameter blocks and main blocks, individual block locking scheme that allows any block to be locked, unlocked or locked-down with no latency. the time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). the block is locked via the set block lock bit command or set block lock-down bit command. block erase, full chip erase and (page buffer) program operation cannot be executed for locked block, to protect codes and data from unwanted operation due to noises, etc. when the wp# pin is at v il , the locked-down block cannot be unlocked. when wp# pin is at v ih , lock- down bits are disabled and any block can be locked or unlocked through software. after wp# goes v il , any block previously marked lock-down revert to that state. at power-up or device reset, all blocks default to locked state and are not locked-down, regardless of the states before power-off or reset operation. this means that all write operations on any block are disabled. unauthorized use of cellular phone, communication device, etc. can be avoided by storing a security code into the 8-word otp (one time program) block (see figure 4) provided in addition to the parameter and main blocks. to ensure high reliability, a lock function for the otp block is provided. the product has a v pp pin which monitors the level of the power supply voltage. when v pp v pplk , memory contents cannot be altered and the data in all blocks are completely write protected (see note 1) . note that the v pp is used only for checking the supply voltage, not used for device power supply pin. automatic power savings (aps) is the low power features to help increase battery life in portable applications. aps mode is initiated shortly after read cycle completion. in this mode, its current consumption decreases to the value equivalent of that in the standby mode. standard address access timings (t avqv ) provide new data when addresses are changed. during dual work operation (one partition being erased or programmed, while other partitions are read modes), the device cannot enter the automatic power savings mode if the input address remains unchanged. a cui (command user interface) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. the product uses an advanced wsm (write state machine) to automatically execute erase and program operations within the memory array. the wsm is controlled through the cui. by writing a valid command sequence to the cui, the wsm is instructed to automatically handle the sequence of internal events and timings required to block erase, full chip erase, (page buffer) program or otp program operations. status registers are prepared for each partition to indicate the status of the partition. even if the wsm is occupied by executing erase or program operation in one partition, the status register of other partition reports that the device is not busy when the device is set to 2, 3 or 4 partitions configuration. (note 1) please note following: for the lockout voltage v pplk to inhibit all write functions, refer to specifications. v pp should be kept lower than v pplk (gnd) during read operations to protect the data in all blocks. rev. 2.44 fum00701 4 when the rst# pin is at v il , reset mode is enabled which minimizes power consumption and provides write protection. the rst# is also useful for resetting the wsm to read array mode and initializing the status register bits to "80h". during power-on/off or transitions, keep the rst# pin at v il level to protect the data from noises, and initialize the device ? s internal control circuit. a reset time (t phqv ) is required from rst# switching high until outputs are valid. likewise, the device has a wake time (t phwl , t phel ) from rst#-high until writes to the cui are recognized. erase operation erases one block or all blocks. programming is executed in either one word increments or by page sized increments using the high speed program page buffers. these operations use an industry standard set of cui command sequences. suspend commands exist for both the erase and program operations to permit the system to interrupt an erase or program operation in progress to enable the access to another memory location in the same partition. nested suspend is also supported. this allows the software to suspend an erase in one partition, start programming in a second partition, suspend programming in the second partition, then read from the second partition. after reading from the second partition, resume the suspended program in the second partition, then resume the suspended erase in the first partition. figure 1 shows the block diagram for the product. the example of pin descriptions are explained in table 3. notes: 1. "x" denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm (write state machine) state - this allows a status register for each partition. only one partition can be erased or programmed at a time - no command queuing. commands must be written to an address within the block targeted by that command. table 2. simultaneous operation modes allowed with four planes (1, 2) if one partition is: then the modes allowed in the other partition is: read array read id/otp read status read query word program page buffer program otp program block erase full chip erase program suspend block erase suspend read arrayxxxx x x x x x read id/otpxxxx x x x x x read statusxxxx x x x x x x x read queryxxxx x x x x x word programxxxx x page buffer program xxxx x otp program x block erasexxxx full chip erase x program suspend xxxx x block erase suspend xxxx x x x rev. 2.44 fum00701 5 main block (n-1) main block 0 main block 1 parameter block 1 parameter block 0 parameter block 2 parameter block 4 parameter block 3 parameter block 7 parameter block 5 parameter block 6 main block n 32k-word main blocks y decoder x decoder y-gating output buffer input buffer output multiplexer identifier codes register i/o logic status register data comparator page buffer command user interface write state machine erase/program voltage switch a 0 -a 20 (32m) dq 0 -dq 15 v cc v cc v pp ce# we# oe# rst# wp# gnd v ccq otp block input buffer multiplexer data register 2 to (n-2) the number of main blocks : n=62 (32mbit) n=126 (64mbit) a 0 -a 21 (64m) partition configuration register query rom block diagram for 32mbit or 64mbit with 16-bit i/o interface and one ce# pin. figure 1. block diagram rev. 2.44 fum00701 6 table 3. pin descriptions symbol type name and function a 0 -a 20 input address inputs: inputs for addresses. 32m: a 0 -a 20 a 0 -a 21 input address inputs: inputs for addresses. 64m or 128m: a 0 -a 21 dq 0 -dq 15 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code, identifier code and partition configuration register code reads. data pins float to high- impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. ce# input chip enable: activates the device ? s control logic, input buffers, decoders and sense amplifiers. ce#-high (v ih ) deselects the device and reduces power consumption to standby levels. rst# input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rst# must be low during power-up/down. oe# input output enable: gates the device ? s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of ce# or we# (whichever goes high first). wp# input write protect: when wp# is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and not locked- down. when wp# is v ih , lock-down is disabled. ry/by# open drain output ready/busy#: indicates the status of the internal wsm (write state machine). when low, wsm is performing an internal operation (block erase, full chip erase, (page buffer) program or otp program). ry/by#-high z indicates that the wsm is ready for new commands, block erase is suspended and (page buffer) program is inactive, (page buffer) program is suspended, or the device is in reset mode. v pp input monitoring power supply voltage: v pp is not used for power supply pin. with v pp v pplk , block erase, full chip erase, (page buffer) program or otp program cannot be executed and should not be attempted. applying 12v0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin. applying 12v0.3v to v pp during erase/program can only be done for a maximum of 1,000 cycles on each block. v pp may be connected to 12v0.3v for a total of 80 hours maximum. use of this pin at 12v beyond these limits may reduce block cycling capability or cause permanent damage. v cc supply device power supply (see specifications): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. v ccq supply input/output power supply (see specifications): power supply for all input/ output pins. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. rev. 2.44 fum00701 7 1.4 product description 1.4.1 memory block organization the device is divided into four physical planes and the partitions can be flexibly configured by the set partition configuration register command. this allows dual work operations, that is, simultaneous read-while-erase and read-while-program operations. for the address locations of the blocks, see the memory map in figure 2.1 through figure 3.2. refer to the specifications for the address locations of the product which has two or more be# (ce#) pins or which has 32-bit i/o interface. 1.4.2 four physical planes the product has four physical planes (one parameter plane and three uniform planes). each plane consists of 8m-bit (32m-bit device) or 16m-bit (64m-bit device) flash memory. the parameter plane consists of eight 4k- word parameter blocks and fifteen (32m-bit device) or thirty-one (64m-bit device) 32k-word main blocks. each uniform plane consists of sixteen (32m-bit device) or thirty-two (64m-bit device) 32k-word main blocks. each block can be erased independently up to 100,000 times. refer to the specifications for the number of planes and each plane density of the product which has two or more be# (ce#) pins or which has 32-bit i/o interface. 1.4.3 partition partition boundaries can be configured by the set partition configuration register command. dual work operation can be done in two partitions. see partition configuration in table 14 and figure 15 for more detail. only one partition can be erased or programmed at a time. simultaneous operation modes are shown in table 2. 1.4.4 parameter block eight 4k-word parameter blocks within the parameter partition are provided as the memory area to facilitate storage of frequently update small parameters that would normally be stored in eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. the protection of the parameter block is controlled using a combination of the v pp , rst#, wp#, block lock bit and block lock-down bit. 1.4.5 main block 32k-word main blocks can store code and/or data. the protection of the main block is also controlled using a combination of the v pp , rst#, wp#, block lock bit and block lock-down bit. 1.4.6 otp (one time program) block the otp block is a special block that cannot be erased in order to secure the high system reliability. this 8-word (128-bit) otp block is independent of main blocks and parameter blocks. figure 4 shows the otp block address map. the otp block is divided into two areas. one is a factory programmed area where a unique number has been programmed in sharp factory. this factory programmed area is "read only" (already locked). the other is a customer programmable area that can be available for customers. this customer programmable area can also be locked. after locking, this customer programmable area is protected permanently. the data within the otp block can be read by the read identifier codes/otp command (90h). to return to read array mode, write the read array command (ffh) to the cui. the otp block bits are programmed by writing the otp program command (c0h) to the cui. write the otp program command (c0h) at the 1st command cycle and then write the address and the data at the 2nd cycle. if the otp program operation is failed, the status register bit sr.4 is set to "1". if the otp block is locked, the status register bits sr.4 and sr.1 are set to "1". the otp block can be locked using the otp program command (c0h). write the otp program command (c0h) at the 1st command cycle and then write the data (fffdh) to the lock location (80h) at the 2nd cycle. read cycle from address (80h) indicates the lockout state of the otp block. bit 0 of address (80h) means the factory programmed area lock state ("1" is "not locked" and "0" is "locked"). bit 1 of address (80h) means the customer programmable lock state. otp block lockout state is not reversible. unlike the main array block lock configuration, the lock state of the otp block is kept unchanged even if the power is turned off or reset operation is performed. the otp program command is only available for programming the otp block. page buffer program operations are available for the main array. otp program cannot be suspended through the (page buffer) program suspend command (described later). dual work operation cannot be executed during otp program. rev. 2.44 fum00701 8 54 53 52 51 50 49 48 55 56 57 58 59 60 61 63 64 65 66 67 68 62 69 70 4k-word 1ff000h - 1fffffh 4k-word 1fe000h - 1fefffh 4k-word 1fd000h - 1fdfffh 4k-word 1fc000h - 1fcfffh 4k-word 1fb000h - 1fbfffh 4k-word 1fa000h - 1fafffh 4k-word plane3 (parameter plane) 1f9000h - 1f9fffh 4k-word 1f8000h - 1f8fffh 32k-word 1f0000h - 1f7fffh 32k-word 1e8000h - 1effffh 32k-word 1e0000h - 1e7fffh 32k-word 1d8000h - 1dffffh 32k-word 1d0000h - 1d7fffh 32k-word 1c8000h - 1cffffh 32k-word 1c0000h - 1c7fffh 32k-word 1b8000h - 1bffffh 32k-word 1b0000h - 1b7fffh 32k-word 1a8000h - 1affffh 32k-word 1a0000h - 1a7fffh 32k-word 198000h - 19ffffh 32k-word 190000h - 197fffh 32k-word 188000h - 18ffffh 32k-word 180000h - 187fffh 32 33 34 35 36 37 38 40 41 42 43 44 45 39 46 47 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word plane2 (uniform plane) 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 0 1 2 3 4 5 6 8 9 10 11 12 13 7 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (uniform plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 32k-word 000000h - 007fffh 16 17 18 19 20 21 22 24 25 26 27 28 29 23 30 31 32k-word 0f8000h - 0fffffh 32k-word 0f0000h - 0f7fffh 32k-word 0e8000h - 0effffh 32k-word 0e0000h - 0e7fffh 32k-word 0d8000h - 0dffffh 32k-word 0d0000h - 0d7fffh 32k-word plane1 (uniform plane) 0c8000h - 0cffffh 32k-word 0c0000h - 0c7fffh 32k-word 0b8000h - 0bffffh 32k-word 0b0000h - 0b7fffh 32k-word 0a8000h - 0affffh 32k-word 0a0000h - 0a7fffh 32k-word 098000h - 09ffffh 32k-word 090000h - 097fffh 32k-word 088000h - 08ffffh 32k-word 080000h - 087fffh block number address range block number address range figure 2.1. memory map for 32mbit (top parameter) rev. 2.44 fum00701 9 6 5 4 3 2 1 0 7 8 9 10 11 12 13 15 16 17 18 19 20 14 21 22 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh 23 24 25 26 27 28 29 31 32 33 34 35 36 30 37 38 32k-word 0f8000h - 0fffffh 32k-word 0f0000h - 0f7fffh 32k-word 0e8000h - 0effffh 32k-word 0e0000h - 0e7fffh 32k-word 0d8000h - 0dffffh 32k-word 0d0000h - 0d7fffh 32k-word plane1 (uniform plane) 0c8000h - 0cffffh 32k-word 0c0000h - 0c7fffh 32k-word 0b8000h - 0bffffh 32k-word 0b0000h - 0b7fffh 32k-word 0a8000h - 0affffh 32k-word 0a0000h - 0a7fffh 32k-word 098000h - 09ffffh 32k-word 090000h - 097fffh 32k-word 088000h - 08ffffh 32k-word 080000h - 087fffh 39 40 41 42 43 44 45 47 48 49 50 51 52 46 53 54 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word plane2 (uniform plane) 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 55 56 57 58 59 60 61 63 64 65 66 67 68 62 69 70 32k-word 1f8000h - 1fffffh 32k-word 1f0000h - 1f7fffh 32k-word 1e8000h - 1effffh 32k-word 1e0000h - 1e7fffh 32k-word 1d8000h - 1dffffh 32k-word 1d0000h - 1d7fffh 32k-word plane3 (uniform plane) 1c8000h - 1cffffh 32k-word 1c0000h - 1c7fffh 32k-word 1b8000h - 1bffffh 32k-word 1b0000h - 1b7fffh 32k-word 1a8000h - 1affffh 32k-word 1a0000h - 1a7fffh 32k-word 198000h - 19ffffh 32k-word 190000h - 197fffh 32k-word 188000h - 18ffffh 32k-word 180000h - 187fffh block number address range block number address range figure 2.2. memory map for 32mbit (bottom parameter) rev. 2.44 fum00701 10 127 128 129 130 131 132 133 4k-word 3ff000h - 3fffffh 4k-word 3fe000h - 3fefffh 4k-word 3fd000h - 3fdfffh 4k-word 3fc000h - 3fcfffh 4k-word 3fb000h - 3fbfffh 4k-word 3fa000h - 3fafffh 4k-word plane3 (parameter plane) 3f9000h - 3f9fffh 3f8000h - 3f8fffh plane2 (uniform plane) 0 1 2 3 4 5 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (uniform plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 32k-word 000000h - 007fffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh plane1 (uniform plane) 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh block number address range block number address range 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 6 8 9 10 11 7 26 28 29 30 31 27 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 4k-word figure 3.1. memory map for 64mbit (top parameter) rev. 2.44 fum00701 11 6 5 4 3 2 1 0 7 4k-word 007000h - 007fffh 4k-word 006000h - 006fffh 4k-word 005000h - 005fffh 4k-word 004000h - 004fffh 4k-word 003000h - 003fffh 4k-word 002000h - 002fffh 4k-word 001000h - 001fffh 4k-word 000000h - 000fffh plane2 (uniform plane) 92 93 94 95 64 65 72 73 74 75 32k-word 278000h - 27ffffh 32k-word 270000h - 277fffh 32k-word 268000h - 26ffffh 32k-word 260000h - 267fffh 32k-word 258000h - 25ffffh 32k-word 250000h - 257fffh 32k-word 248000h - 24ffffh 32k-word 240000h - 247fffh 32k-word 238000h - 23ffffh 32k-word 230000h - 237fffh 32k-word 228000h - 22ffffh 32k-word 220000h - 227fffh 32k-word 218000h - 21ffffh 32k-word 210000h - 217fffh 32k-word 208000h - 20ffffh 32k-word 200000h - 207fffh 2f8000h - 2fffffh 2f0000h - 2f7fffh 2e8000h - 2effffh 2e0000h - 2e7fffh 2d8000h - 2dffffh 2d0000h - 2d7fffh 2c8000h - 2cffffh 2c0000h - 2c7fffh 2b8000h - 2bffffh 2b0000h - 2b7fffh 2a8000h - 2affffh 2a0000h - 2a7fffh 298000h - 29ffffh 290000h - 297fffh 288000h - 28ffffh 280000h - 287fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 76 78 79 80 81 82 83 77 84 85 66 68 69 70 71 67 86 88 89 90 91 87 plane1 (uniform plane) block number address range 62 63 32 33 34 35 42 43 44 45 32k-word 178000h - 17ffffh 32k-word 170000h - 177fffh 32k-word 168000h - 16ffffh 32k-word 160000h - 167fffh 32k-word 158000h - 15ffffh 32k-word 150000h - 157fffh 32k-word 148000h - 14ffffh 32k-word 140000h - 147fffh 32k-word 138000h - 13ffffh 32k-word 130000h - 137fffh 32k-word 128000h - 12ffffh 32k-word 120000h - 127fffh 32k-word 118000h - 11ffffh 32k-word 110000h - 117fffh 32k-word 108000h - 10ffffh 32k-word 100000h - 107fffh 1f8000h - 1fffffh 1f0000h - 1f7fffh 1e8000h - 1effffh 1e0000h - 1e7fffh 1d8000h - 1dffffh 1d0000h - 1d7fffh 1c8000h - 1cffffh 1c0000h - 1c7fffh 1b8000h - 1bffffh 1b0000h - 1b7fffh 1a8000h - 1affffh 1a0000h - 1a7fffh 198000h - 19ffffh 190000h - 197fffh 188000h - 18ffffh 180000h - 187fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 46 48 49 50 51 52 53 47 54 55 36 38 39 40 41 37 56 58 59 60 61 57 12 13 14 15 32k-word 078000h - 07ffffh 32k-word 070000h - 077fffh 32k-word 068000h - 06ffffh 32k-word 060000h - 067fffh 32k-word 058000h - 05ffffh 32k-word 050000h - 057fffh 32k-word plane0 (parameter plane) 048000h - 04ffffh 32k-word 040000h - 047fffh 32k-word 038000h - 03ffffh 32k-word 030000h - 037fffh 32k-word 028000h - 02ffffh 32k-word 020000h - 027fffh 32k-word 018000h - 01ffffh 32k-word 010000h - 017fffh 32k-word 008000h - 00ffffh 0f8000h - 0fffffh 0f0000h - 0f7fffh 0e8000h - 0effffh 0e0000h - 0e7fffh 0d8000h - 0dffffh 0d0000h - 0d7fffh 0c8000h - 0cffffh 0c0000h - 0c7fffh 0b8000h - 0bffffh 0b0000h - 0b7fffh 0a8000h - 0affffh 0a0000h - 0a7fffh 098000h - 09ffffh 090000h - 097fffh 088000h - 08ffffh 080000h - 087fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 16 18 19 20 21 22 23 17 24 25 8 9 10 11 26 28 29 30 31 27 127 128 129 130 131 132 133 32k-word plane3 (uniform plane) 3f8000h - 3fffffh 122 123 124 102 103 104 105 32k-word 378000h - 37ffffh 32k-word 370000h - 377fffh 32k-word 368000h - 36ffffh 32k-word 360000h - 367fffh 32k-word 358000h - 35ffffh 32k-word 350000h - 357fffh 32k-word 348000h - 34ffffh 32k-word 340000h - 347fffh 32k-word 338000h - 33ffffh 32k-word 330000h - 337fffh 32k-word 328000h - 32ffffh 32k-word 320000h - 327fffh 32k-word 318000h - 31ffffh 32k-word 310000h - 317fffh 32k-word 308000h - 30ffffh 32k-word 300000h - 307fffh 3f0000h - 3f7fffh 3e8000h - 3effffh 3e0000h - 3e7fffh 3d8000h - 3dffffh 3d0000h - 3d7fffh 3c8000h - 3cffffh 3c0000h - 3c7fffh 3b8000h - 3bffffh 3b0000h - 3b7fffh 3a8000h - 3affffh 3a0000h - 3a7fffh 398000h - 39ffffh 390000h - 397fffh 388000h - 38ffffh 380000h - 387fffh 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 32k-word 106 108 109 110 111 112 113 107 114 115 96 98 99 100 101 97 116 118 119 120 121 117 125 126 134 block number address range figure 3.2. memory map for 64mbit (bottom parameter) rev. 2.44 fum00701 12 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000088h [a 21 -a 0 ] (dq 15 -dq 2) figure 4. otp block address map for otp program (1, 2) (the area outside 80h~88h cannot be used.) notes: 1. a 21 is not used for 32m-bit device. 2. refer to table 6 through table 8 as to the otp block address map for read operation. rev. 2.44 fum00701 13 2 principles of operation the product includes an on-chip wsm (write state machine) and can automatically execute block erase, full chip erase, (page buffer) program or otp program operation after writing the proper command to the cui (command user interface). 2.1 operation mode after power-up or reset mode after initial power-up or reset mode (refer to bus operation in section 3), the device defaults to the following mode. asynchronous read mode in which 8-word page mode is available plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. all blocks default to locked state and are not locked- down. manipulation of external memory control pins (ce#, oe#) allow read array, standby and output disable modes. 2.2 read, program and erase operation independent of the v pp voltage, the memory array, status register, identifier codes, otp block and query codes can be accessed. and also, set/clear block lock configuration and set partition configuration register are available even if the v pp voltage is lower than v pplk . applying the specified voltage on v cc and v pph1/2 on v pp enables successful block erase, (page buffer) program and otp program operation. applying the specified voltage on v cc and v pph1 on v pp enables successful full chip erase operation. all functions associated with altering memory contents, which is block erase, full chip erase, (page buffer) program and otp program, are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. addresses and data are internally latched on the rising edge of ce# or we# whichever goes high first during command write cycles. the cui contents serve as input to the wsm, which controls block erase, full chip erase, (page buffer) program and otp program. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. writing the appropriate command outputs array data, status register data, identifier codes, lock configuration codes, device configuration codes, data within the otp block and query codes. in any block, the user can store an interface software that initiates and polls progress of block erase or (page buffer) program. because the product has dual work function, data can be read from the partition not being erased or programmed without using the block erase suspend or (page buffer) program suspend. when the target partition is being erased or programmed, block erase suspend or (page buffer) program suspend allows system software to read/program data from/to blocks other than that which is suspended. 2.3 status register for each partition the product has status registers for each partition. the 8- bit status register is available to monitor the partition state, or the erase or program status. status register indicates the status of the partition, not wsm. even if the status register bit sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. the status register reports if an erase or program operation to each partition has been successfully completed, and if not, indicates a reason for the error. this register cannot be set, only can be cleared by writing the clear status register command or by resetting the device. 2.4 data protection block lock bit and block lock-down bit can be set for each block, to protect the data within its block. if the rst# is driven low (v il ), or if the voltage on the v cc pin is below the write lock out voltage (v lko ), or if the voltage on the v pp pin is below the write lock out voltage (v pplk ), then all write functions including otp program are disabled. the system should be designed to switch the voltage on v pp below the write lock out voltage (v pplk ) for read cycles. this scheme provides the data protection at the hardware level. the two-cycle command sequence architecture for block erase, full chip erase, (page buffer) program, otp program, and block lock configuration provides the data protection at the software level against data alternation. rev. 2.44 fum00701 14 3 bus operation the system cpu reads and writes the flash memory. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. table 4 lists the bus operation. the function which is available varies according to each product. refer to the specifications whether each function in this document is available or not. the function which is not described in the specifications can not be used for that product, even if that function is explained in this section. 3.1 read array the product has five control pins (ce#, oe#, we#, rst# and wp#). when rst# is v ih , read operations access the memory array, status register, identifier codes, otp block and query codes independent of the voltage on v pp . the device is automatically initialized upon power-up or device reset mode and set to asynchronous read mode in which 8-word page mode is available. as necessary, write the appropriate read command (read array, read identifier codes/otp, read query or read status register command) with the partition address to the cui (command user interface). the cui decodes the partition address and set the target partition to the appropriate read mode. asynchronous page mode is available only for main array, that is, parameter blocks and main blocks. read operations for status register, identifier codes, otp block and query codes support single asynchronous read cycle. to read data from the product, rst# and we# must be at v ih , and ce# and oe# at v il . ce# is the device selection control, and ce#-low enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and oe#-low drives the selected memory data onto the i/o bus. 3.2 output disable with oe# at v ih , the device outputs are disabled. output pins dq 0 - dq 15 are placed in a high-impedance (high z) state. 3.3 standby ce# at a logic-high level (v ih ) places the product in standby mode. in standby mode, the product substantially reduces its power consumption because almost of all internal circuits are inactive. dq 0 -dq 15 outputs a high z state independent of oe#. even if ce# is set to v ih during block erase, full chip erase, (page buffer) program or otp program, the device continues the operation and consumes active power until the completion of the operation. 3.4 reset driving rst# to logic-low level (v il ) places the product in reset mode. if rst# is held v il for a minimum t plph in read modes, the device is deselected and internal circuitry is turned off. outputs are placed in a high z state. status register is set to 80h. time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the device returns to the initial mode described in section 2.1. during block erase, full chip erase, (page buffer) program or otp program mode, rst#-low will abort the operation. memory contents being altered are no longer valid; the data may be partially erased or programmed. status register bit sr.7 remains "0" until the reset operation has been completed. after rst# goes to v ih , time t phwl and t phel is required before another command can be written. as with any automated device, it is important to assert rst# during system reset. when the system comes out of reset, it expects to read the data from the flash memory. the product allows proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same reset# signal that resets the system cpu. after return from reset mode, the product is automatically set to asynchronous read mode in which 8-word page mode is available. delay time t phqv is required until memory access outputs are valid. rev. 2.44 fum00701 15 rev. 2.44 notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. rst# at gnd0.2v ensures the lowest power consumption. 4. command writes involving block erase, (page buffer) program or otp program are reliably executed when v pp =v pph1/2 and v cc is the specified voltage. command writes involving full chip erase are reliably executed when v pp =v pph1 and v cc is the specified voltage. 5. refer to table 5 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. refer to section 6 for more information about query code. 8. ry/by# is v ol when the wsm (write state machine) is executing internal block erase, full chip erase, (page buffer) program or otp program algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode. 3.5 read identifier codes/otp the manufacturer code, device code, block lock configuration codes, partition configuration register code and the data within the otp block can be read in the read identifier codes/otp mode (see table 6 through table 8). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. 3.6 read query cfi (common flash interface) code, which is called query code, can be read after writing the read query command. the address to read query code should be in the partition address which is written with the read query command. the cfi data structure contains information such as block size, density, command set and electrical specifications (see section 6). in this mode, read cycles retrieve cfi information. to return to read array mode, write the read array command (ffh) with the partition address. table 4. bus operation (1, 2) mode notes rst# ce# oe# we# address v pp dq 0-15 ry/by# (8) read array 6 v ih v il v il v ih xxd out x output disable v ih v il v ih v ih x x high z x standby v ih v ih xxxxhigh zx reset 3 v il x x x x x high z high z read identifier codes/otp 6 v ih v il v il v ih see table 6 through table 8 x see table 6 through table 8 x read query 6,7 v ih v il v il v ih see section 6 x see section 6 x write 4,5,6 v ih v il v ih v il xxd in x fum00701 16 3.7 write the command to the cui except for the full chip erase command, writing commands to the cui always requires the word address, block address or partition address. before writing the block erase command, full chip erase command, (page buffer) program command or otp program command, wsm (write state machine) should be ready and not be used in any partition. applying the specified voltage on v cc and v pph1/2 on v pp enables successful block erase, (page buffer) program or otp program with writing the proper command and address to the cui. applying the specified voltage on v cc and v pph1 on v pp enables successful full chip erase with writing the proper command to the cui. erase or program operation may occur in only one partition at a time. other partitions must be in one of the read modes. the block erase command requires appropriate command and an address within the block to be erased. the full chip erase command requires appropriate command. the (page buffer) program command requires appropriate command and an address of the location to be programmed. the set/clear block lock bit or set block lock-down bit command requires appropriate command and an address within the target block. the otp program command requires appropriate command and an address of the location to be programmed within the otp block. the set partition configuration register command requires appropriate command and configuration register code presented on the addresses a 0 -a 15 . the cui itself does not occupy an addressable memory location. when both ce# and we# go v il (valid), the command is written to cui and the address and data are latched on the rising edge of ce# or we#, whichever goes high first. the command can be written to the cui at the standard microprocessor writing timing. rev. 2.44 fum00701 17 4 command definitions operations of the device are selected by the specific commands written to the cui (command user interface). since commands are partition-specific, it is important to write commands within the target partition ? s address range (see table 5). the command which is available varies according to each product. refer to the specifications whether each command in this document is available or not. the command which is not described in the specifications can not be used for that product, even if that command is explained in this section. 4.1 how to write the command 4.1.1 using dual work operation the product supports dual work operation and the customer can store a flash memory interface software in the internal memory array of this device. to enable the flash memory interface software to be read at any time, the partition in which the flash memory interface software is stored must remain in the read array mode. therefore, any command except for the read array command, the full chip erase command (refer to section 4.1.3) and the otp program command (refer to section 4.1.3) must be written to the partition in which the flash memory interface software is not stored. for example, when the device is divided into two partitions such as partition 0, partition 1 and the flash memory interface software is stored in the partition 0, any command except for the commands mentioned above must be written to the partition 1. the following describes the reasons. all addresses which are written at the first cycle should be the same as the addresses which are written at the second cycle. all the commands except for the full chip erase command and the otp program command require the partition address. partition address (refer to figure 2.1 through figure 3.2 for the memory map) a 20 -a 16 (32m-bit device) a 21 -a 16 (64m-bit or 128m-bit device) when the command is written, the partition address must be placed on the address bus a 20 -a 16 or a 21 - a 16 at the first, second and subsequent command cycle. each command except for the full chip erase command and the otp program command affects only the mode of the partition to which the command is written. after the first cycle command of block erase (20h), program (40h or 10h), set/clear block lock bit (60h), set block lock-down bit (60h), or set partition configuration register (60h) is written, the target partition to which the command is written is put into the read status register mode. subsequent read operations to that partition output the status register data of its partition. after the first cycle command of page buffer program (e8h) is written, the target partition to which the command is written is put into the read extended status register mode. subsequent read operations to that partition output the extended status register data. after the second cycle command of block erase (d0h), program (data to be programmed), set block lock bit (01h), clear block lock bit (d0h) or set block lock-down bit (2fh) is written, the target partition to which the command is written remains in the read status register mode. after the second cycle command of set partition configuration register (04h) is written and the operation is successfully completed, all the partitions return to the read array mode. if the operation is not completed successfully, the target partition to which the command is written remains in the read status register mode. after the second and subsequent cycle commands of page buffer program are written, the target partition to which the command is written is put into the read status register mode. subsequent read operations to that partition output the status register data of its partition. rev. 2.44 fum00701 18 4.1.2 not using dual work operation in this case, the flash memory interface software must be stored in the external rom area. the command can be written to any partition. however, all first and second cycle command addresses should be the same and the commands require the partition address. 4.1.3 full chip erase and otp program full chip erase and otp program are different from other modes, in which dual work operation is not available. the following describes the reasons. after the first cycle command of full chip erase (30h) or otp program (c0h) is written to any partition, all the partitions are put into the read status register mode. subsequent read operations to any partition output the status register data. the memory array data cannot be read in these modes. after the second cycle command of full chip erase (d0h) or otp program (data to be programmed) is written to any partition, all the partitions remain in the read status register mode. subsequent read operations to any partition output the status register data. the memory array data cannot be read in these modes. to read the memory array data, write the read array command (ffh) after the full chip erase or otp program operation has been successfully completed. when full chip erase or otp program operation is used, the customer must store the flash memory interface software that initiates and polls progress of full chip erase or otp program to the external rom area. 4.2 read array command upon initial device power-up or after reset mode, all the partitions in the device default to asynchronous read mode in which 8-word page mode is available. the read array command to a partition places the partition to read array mode. the partition remains enabled for read array mode until another valid command is written to the partition. when rst# is at v ih , the read array command is valid independent of the voltage on v pp . once the internal wsm (write state machine) has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read array command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read array command can be accepted in other partitions except for full chip erase or otp program operation. since the product provide dual work capability, partitions not executing block erase or (page buffer) program operation are allowed to set to the read array mode and the memory array data within the partitions can be read without suspending block erase or (page buffer) program operation. 4.3 read identifier codes/otp command the read identifier codes/otp mode is initiated by writing the read identifier codes/otp command (90h) to the target partition. read operations to that partition output the identifier codes or the data within the otp block. to terminate the operation, write another valid command to the partition. in this mode, the manufacturer code, device code, block lock configuration codes, partition configuration register code and the data within the otp block as well as the otp block lock state can be read on the addresses shown in table 6 through table 8. once the internal wsm has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read identifier codes/otp command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read identifier codes/ otp command can be accepted in other partitions except for full chip erase or otp program operation. like the read array command, the read identifier codes/otp command functions independently of the v pp voltage and rst# must be at v ih . to read the data in the otp block, it is important to write addresses within the otp area ? s address range (refer to table 6 through table 8). asynchronous page mode is not available for reading identifier codes/otp. read operations for identifier codes or otp block support single asynchronous read cycle. rev. 2.44 fum00701 19 notes: 1. bus operations are defined in table 4. 2. all addresses which are written at the first bus cycle should be the same as the addresses which are written at the second bus cycle. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see table 6 through table 8). qa=query codes address. refer to section 6 for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see figure 4). pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes. (see table 6 through table 8). qd=data read from query database. refer to section 6 for details. srd=data read from status register. see table 9 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. od=data within otp block. data is latched on the rising edge of we# or ce# (whichever goes high first) during command write cycles. n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within otp block (see table 6 through table 8). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rst# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, input the program sequential address and write data of "n" times. finally, input the any valid address within the target block to be programmed and the confirm command (d0h). refer to section 4.10 for table 5. command definitions (11) command bus cycles req ? d notes first bus cycle second bus cycle oper (1) addr (2) data oper (1) addr (2) data (3) read array 1 write pa ffh read identifier codes/otp 2 4 write pa 90h read ia or oa id or od read query 24writepa 98hreadqa qd read status register 2 write pa 70h read pa srd clear status register 1 write pa 50h block erase 2 5 write ba 20h write ba d0h full chip erase 2 5,9 write x 30h write x d0h program 25,6writewa 40h or 10h write wa wd page buffer program 4 5,7 write wa e8h write wa n-1 block erase and (page buffer) program suspend 18,9writepa b0h block erase and (page buffer) program resume 18,9writepa d0h set block lock bit 2 write ba 60h write ba 01h clear block lock bit 2 10 write ba 60h write ba d0h set block lock-down bit 2 write ba 60h write ba 2fh otp program 2 9 write oa c0h write oa od set partition configuration register 2 write pcrc 60h write pcrc 04h rev. 2.44 fum00701 20 details. 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp# is v il . when wp# is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 2.44 fum00701 21 notes: 1. the address a 21 , a 20 -a 16 are shown in below table for reading the manufacturer code, device code, device configuration code and otp data. 2. top parameter device has its parameter blocks in the plane3 (the highest address). bottom parameter device has its parameter blocks in the plane0 (the lowest address). 3. block address = the beginning location of a block address within the partition to which the read identifier codes/otp command (90h) has been written. dq 15 -dq 2 are reserved for future implementation. 4. pcrc=partition configuration register code. 5. otp-lk=otp block lock configuration. 6. otp=otp block data. notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). 2. refer to table 14 for the partition configuration register. table 6. identifier codes and otp address for read operation code address [a 15 -a 0 ] data [dq 15 -dq 0 ] notes manufacturer code manufacturer code 0000h 00b0h 1 device code top parameter device code 0001h refer to specifications 1, 2 bottom parameter device code 0001h 1, 2 block lock configuration code block is unlocked block address + 2 dq 0 = 0 3 block is locked dq 0 = 1 3 block is not locked-down dq 1 = 0 3 block is locked-down dq 1 = 1 3 device configuration code partition configuration register 0006h pcrc 1, 4 otp otp lock 0080h otp-lk 1, 5 otp 0081-0088h otp 1, 6 table 7. identifier codes and otp address for read operation on partition configuration (1) (32m-bit device) partition configuration register (2) address (32m-bit device) pcr.10 pcr.9 pcr.8 [a 20 -a 16 ] 00000h 0 0 1 00h or 08h 0 1 0 00h or 10h 1 0 0 00h or 18h 0 1 1 00h or 08h or 10h 1 1 0 00h or 10h or 18h 1 0 1 00h or 08h or 18h 1 1 1 00h or 08h or 10h or 18h rev. 2.44 (7) 7. refer to the specifications for the information of the product which has two or more be# (ce#) pins or which has 32-bit i/o interface. fum00701 22 notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). 2. refer to table 14 for the partition configuration register. table 8. identifier codes and otp address for read operation on partition configuration (1) (64m-bit device) partition configuration register (2) address (64m-bit device) pcr.10 pcr.9 pcr.8 [a 21 -a 16 ] 00000h 0 0 1 00h or 10h 0 1 0 00h or 20h 1 0 0 00h or 30h 0 1 1 00h or 10h or 20h 1 1 0 00h or 20h or 30h 1 0 1 00h or 10h or 30h 1 1 1 00h or 10h or 20h or 30h rev. 2.44 fum00701 23 4.4 read query command the read query mode is initiated by writing the read query command (98h) to the target partition. read operations to that partition output the query code (common flash interface code) shown in section 6. to terminate the operation, write another valid command to the partition. once the internal wsm has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read query command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read query command can be accepted in other partitions except for full chip erase or otp program operation. like the read array command, the read query command functions independently of the v pp voltage and rst# must be at v ih . refer to section 6 for more information about query code. asynchronous page mode is not available for reading query code. read operations for query code support single asynchronous read cycle. 4.5 read status register command the status register may be read to determine when block erase, full chip erase, (page buffer) program or otp program has been completed and whether the operation has been successfully completed or not (see table 9). the status register can be read at any time by writing the read status register command (70h) to the target partition. subsequent read operations to that partition output the status register data until another valid command is written. the status register contents are latched on the falling edge of oe# or ce# whichever occurs later. this requires address setup time (t avgl or t av e l ) to and address hold time (t glax or t elax ) from the later falling edge of oe# or ce#. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage and rst# must be at v ih . asynchronous page mode is not available for reading status register. read operations for status register support single asynchronous read cycle. during the dual work operation, the status register data is read from the partition which is executing block erase or (page buffer) program operation. the memory array data can be read from other partitions which are not executing block erase or (page buffer) program operation. the partition to be accessed is automatically identified according to the input address. 4.6 clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 that have been set to "1"s by the wsm can only be cleared by writing the clear status register command (50h). this command functions independently of the v pp voltage. rst# must be at v ih . to clear the status register, write the clear status register command and an address within the target partition to the cui. status register bits sr.5, sr.4, sr.3 and sr.1 indicate various error conditions occurring after writing commands (see table 9). when erasing multiple blocks or programming several words in sequence, clear these bits before starting each operation. the status register bits indicate an error for during the sequence. after executing the clear status register command, the partition returns to read array mode. this command clears only the status register of the addressed partition. during block erase suspend or (page buffer) program suspend, the clear status register command is invalid and the status register cannot be cleared. rev. 2.44 fum00701 24 table 9. status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess befces pbpops vpps pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (page buffer) program and otp program status (pbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = v pp status (vpps) 1 = v pp low detect, operation abort 0 = v pp ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 or ry/by# to determine block erase, full chip erase, (page buffer) program or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, set partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when v pp v pph1 , v pph2 or v pplk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are reserved for future use and should be masked out when polling the status register. rev. 2.44 fum00701 25 table 10. extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7="1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. rev. 2.44 fum00701 26 4.7 block erase command the two-cycle block erase command initiates one block erase at the addressed block within the target partition. read operations to that partition output the status register data of its partition. at the first cycle, command (20h) and an address within the block to be erased is written to the cui, and command (d0h) and the same address as the first cycle is written at the second cycle. once the block erase command is successfully written, the wsm automatically starts erase and verification processes. the data in the selected block are erased (becomes ffffh). the system cpu can detect the block erase completion by analyzing the output data of the status register bit sr.7. the partition including the block to be erased remains in read status register mode after the completion of the block erase operation until another command is written to the cui. figure 5.1 and figure 5.2 show a flowchart of the block erase operation. check the status register bit sr.5 at the end of block erase. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the partition remains in read status register mode until a new command is written to that partition. this two-cycle command sequence ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in status register bits sr.5 and sr.4 of the partition being set to "1" and the operation will be aborted. for reliable block erase operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, block erase operations are not guaranteed. for example, attempting a block erase at v pp v pplk causes sr.5 and sr.3 being set to "1". also, successful block erase requires that the selected block is unlocked. when block erase is attempted to the locked block, bits sr.5 and sr.1 will be set to "1". block erase operation may occur in only one partition at a time. other partitions must be in one of the read modes. 4.8 full chip erase command the two-cycle full chip erase command erases all of the unlocked blocks. before writing this command, all of the partitions should be ready (wsm should not be occupied by any partition). at the first cycle, command (30h) is written to the cui, and command (d0h) is written at the second cycle. after writing the command, the device outputs the status register data when any address within the device is selected. the wsm automatically starts the erase operation for all unlocked blocks, skipping the locked blocks. the full chip erase operation cannot be suspended through the erase suspend command (described later). the system cpu can detect the full chip erase completion by analyzing the output data of the status register bit sr.7. all the partitions remain in the read status register mode after the completion of the full chip erase operation until another command is written to the cui. figure 6.1 and figure 6.2 show a flowchart of the full chip erase operation. the wsm aborts the operation upon encountering an error during the full chip erase operation and leaves the remaining blocks not erased. after the full chip erase operation, check the status register bit sr.5. when a full chip erase error is detected, sr5 of all partitions will be set to "1". the status registers for all partitions should be cleared before system software attempts corrective actions. after that, retry the full chip erase command or erase block by block using the block erase command. this two-cycle command sequence ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in status register bits sr.5 and sr.4 of all partitions being set to "1" and the operation will be aborted. for reliable full chip erase operation, apply the specified voltage on v cc and v pph1 on v pp . in the absence of this voltage, full chip erase operations are not guaranteed. for example, attempting a full chip erase at v pp v pplk causes sr.5 and sr.3 being set to "1". the full chip erase operation with applying v pph2 on v pp is inhibited for some products. refer to the specifications whether the full chip erase operation with applying v pph2 on v pp is available or not. as previously mentioned, the full chip erase command erases all blocks except for the locked blocks. unlike the block erase, the status register bits sr.5 and sr.1 are not set to "1" even if the locked block is included. however, when all blocks are locked, the bits sr.5 and sr.1 are set to "1" and the operation will not be executed. if an error is detected during the full chip erase operation, error bits for status registers in all partitions are set to "1". this requires that the clear status register command be written to all partitions to clear the error bits. dual work operation is not available during the full chip erase mode. the memory array data cannot be read in this mode. to return to the read array mode, write the read array command (ffh) to the cui after the completion of the full chip erase operation. rev. 2.44 fum00701 27 sr.7= 0 1 write d0h, block address write 20h, block address read status register, block address suspend block erase loop full status check if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions if desired status check for all partitions before block erase operation for all partitions status check procedure block erase complete start block erase suspend yes no exist? another partition yes no suspended (page buffer) program should be resumed first suspended block erase should be resumed first sr.7= 0 1 sr.2= 1 0 sr.6= 1 0 complete bus operation command comments write block erase fum00701 28 block erase successful read status register data full status check procedure sr.3= 1 0 v pp range error sr.1= 1 0 device protect error command sequence error sr.4,5= 1 0 sr.5= 1 0 block erase error figure 5.2. automated block erase flowchart (continued) rev. 2.44 bus operation command comments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4,5 both 1=command sequence error standby check sr.5 1=block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. fum00701 29 write 30h write d0h read status register sr.7= 0 1 full status check if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions if desired status check for all partitions before full chip erase operation for all partitions status check procedure full chip erase complete start exist? another partition yes no suspended (page buffer) program should be resumed first suspended block erase should be resumed first sr.7= 0 1 sr.2= 1 0 sr.6= 1 0 complete bus operation command comments write full chip erase fum00701 30 full chip erase successful read status register data full status check procedure sr.3= 1 0 v pp range error sr.1= 1 0 device protect error command sequence error sr.4,5= 1 0 sr.5= 1 0 full chip erase error bus operation command comments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect all blocks are locked. standby check sr.4,5 both 1=command sequence error standby check sr.5 1=full chip erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 6.2. automated full chip erase flowchart (continued) rev. 2.44 fum00701 31 4.9 program command a two-cycle command sequence written to the target partition initiates a word program operation. read operations to the target partition to be programmed output the status register data until another valid command is written. at the first cycle, write command (standard 40h or alternate 10h) and an address of memory location to be programmed, followed by the second write that specifies the address and data. the wsm then takes over, controlling the internal word program algorithm. the system cpu can detect the word program completion by analyzing the output data of the status register bit sr.7. figure 8.1 and figure 8.2 show a program flowchart. the internal wsm verify only detects errors for "1"s that are not successfully programmed to "0"s. check the status register bit sr.4 at the end of word program. if a word program error is detected, the status register should be cleared before system software attempts corrective actions. the partition remains in read status register mode until it receives another command. for reliable word program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, word program operations are not guaranteed. for example, attempting a word program at v pp v pplk causes sr.4 and sr.3 being set to "1". also, successful word program requires for the selected block is unlocked. when word program is attempted to the locked block, bits sr.4 and sr.1 will be set to "1". word program operation may occur in only one partition at a time. other partitions must be in one of the read modes. 4.10 page buffer program command the product has 16-word page buffer, which can perform fast sequential programming up to 16 words. however, this 16-word address must be inside every 4k-word address range xxx000h-xxxfffh, as shown in figure 7. when programming across this 4k-word address range, sequence error occurs and status register bits sr.5 and sr.4 are set to "1". the data are once loaded to the page buffer and programmed to the flash array when the confirm command (d0h) is written. see the flowchart in figure 9.1 and figure 9.2. the page buffer program is executed by at least four- cycle or up to 19-cycle command sequence. first, write the page buffer program setup command (e8h) and start address to the partition ? s cui. at this point, read operations to the target partition to be programmed output the extended status register data (see table 10). check the extended status register data. when xsr.7 is set to "1", the setup command written is valid. then, at the second cycle, write the word count [n]-1 and start address if the number of words to be programmed is [n] in total. that is, when the number of [n] is 1 word, write (00h); if [n] is 16 words, write (0fh). the word count [n]-1 must be less than or equal to 0fh. attempting to write more than 0fh for the word count causes the sequence error and the status register bits sr.5 and sr.4 are set to "1". after writing a word count [n]-1, read operations to the target partition to be programmed output the status register data. at the third cycle following the write of [n]-1, write the first data to be programmed and start address to the partition ? s cui. lower 4 bits (a 0 -a 3 ) of the start address also correspond to the page buffer address and the data are stored in the page buffer. at the fourth and subsequent cycles, write additional data and address, depending on the count. all subsequent address must lie within the start address plus the count. after writing the nth word data, write the confirm command (d0h) and an address within the target block to be programmed at the last cycle. this initiates the wsm to being transferring the data from the page buffer to the flash array. if a command other than the confirm command (d0h) is written, sequence error occurs and status register bits sr.5 and sr.4 of the partition are set to "1". when the data are transferred from the page buffer to the flash array, the status register bit sr.7 is set to "0". then, the target partition is in the page buffer program busy mode. rev. 2.44 fum00701 32 4k-word xx7000h - xx7fffh 4k-word xx6000h - xx6fffh 4k-word xx5000h - xx5fffh 4k-word xx4000h - xx4fffh 4k-word xx3000h - xx3fffh 4k-word xx2000h - xx2fffh 4k-word xx1000h - xx1fffh 4k-word xx0000h - xx0fffh address range 16-word page buffer if the page buffer program command is attempted past an erase block boundary, the device will program the data to the flash array up to an erase block boundary and then stop programming. the status register bits sr.5 and sr.4 will be set to "1" (command sequence error). sr.5 and sr.4 should be cleared before writing next command. for reliable page buffer program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, page buffer program operations are not guaranteed. for example, attempting a page buffer program at v pp v pplk causes sr.4 and sr.3 being set to "1". also, successful page buffer program requires for the selected block is unlocked. when page buffer program is attempted to the locked block, bits sr.4 and sr.1 will be set to "1". during page buffer program, dual work operation is available. the array data can be read from partitions not being programmed. page buffer program operation may occur in only one partition at a time. other partitions must be in one of the read modes. rev. 2.44 figure 7. 32k-word block fum00701 33 sr.7= 0 1 write word data and address write 40h or 10h, word address read status register, word address suspend word program loop full status check if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions if desired status check for all partitions before word program operation for all partitions status check procedure word program complete start word program suspend yes no exist? another partition yes no suspended program operation should be resumed first sr.7= 0 1 sr.2= 1 0 complete bus operation command comments write wor d program fum00701 34 word program successful read status register data full status check procedure sr.3= 1 0 v pp range error sr.1= 1 0 device protect error sr.4= 1 0 word program error bus operation command comments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4 1=word program error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 8.2. automated program flowchart (continued) rev. 2.44 fum00701 35 x=1 x=x+1 write d0h xsr.7= 0 1 write buffer time out yes no sr.7= 0 1 page buffer program suspend yes no buffer write command? abort yes no read extended status register write e8h, start address write buffer data, start address write buffer data, address read status register, partition address write another block address full status check if desired status check for all partitions if desired write [word count n]-1, start address start complete page buffer program abort page buffer program x=n yes no suspend page buffer program loop bus operation command comments write page buffer program fum00701 36 set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions page buffer program operation for all partitions before status check procedure exist? another partition yes no suspended program operation should be resumed first sr.7= 0 1 sr.2= 1 0 complete page buffer program successful read status register data page buffer program operation full status check procedure for sr.3= 1 0 v pp range error sr.1= 1 0 device protect error command sequence error sr.4,5= 1 0 sr.4= 1 0 page buffer program error bus operation command comments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.2 1=program suspended 0=program completed bus operation command comments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4,5 both 1=command sequence error standby check sr.4 1=page buffer program error sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 9.2. automated page buffer program flowchart (continued) rev. 2.44 fum00701 37 4.11 block erase suspend command and block erase resume command the block erase suspend command (b0h) allows block erase interruption to read or program data in the blocks other than that which is suspended. this command is valid for the block erase operation and the full chip erase operation can not be suspended. once the block erase process starts in a partition, writing the block erase suspend command to the partition requests that the wsm suspends the block erase sequence at a predetermined point in the algorithm. read operations to the target partition after writing the block erase suspend command access the status register. status register bits sr.7 and sr.6 indicate if the block erase operation has been suspended (both will be set to "1"). specification t whrh2 or t ehrh2 defines the block erase suspend latency. when the block erase suspend command is written after the completion of the block erase operation, the partition returns to read array mode. therefore, the read status register command (70h) must be written to the target partition after writing the block erase suspend command. if the status register bits sr.7 and sr.6 are set to "1", block erase has been suspended. at this point, a read array command can be written to read data from blocks other than that which is suspended. a (page buffer) program command sequence can also be written during block erase suspend to program data in other blocks. using the (page buffer) program suspend command (see section 4.12), a program operation can also be suspended during a block erase suspend. during a word program operation with block erase suspended, status register bit sr.7 will return to "0". however, sr.6 will remain "1" to indicate the block erase suspend status. if the page buffer program setup command (e8h) is written to the target partition during block erase suspend in which sr.7 and sr.6 are set to "1", read operations to the target partition to be programmed output the extended status register data. in read extended status register mode, bit xsr.7 is only valid, which indicates that the written command (e8h) is available, and other bits (from xsr.6 to xsr.0) are invalid (see table 10). when writing the word count [n]-1 and start address at next command cycle, the target partition returns to read status register mode and the status register bits sr.7 and sr.6 are set to "1". after the page buffer program confirm command (d0h) is written, the status register bit sr.7 will return to "0". however, sr.6 will remain "1" to indicate the block erase suspend status. the valid commands while block erase is suspended are read array, read identifier codes/otp, read query, read status register, (page buffer) program, set block lock bit, clear block lock bit, set block lock-down bit and block erase resume command. the commands other than those mentioned above are not accepted and should not be used during a block erase suspend. to resume the block erase operation, write the block erase resume command (d0h) to the partition. status register bits sr.7 and sr.6 will be automatically cleared. after the block erase resume command is written, the target partition automatically outputs the status register data when read. v pp must remain at v pph1/2 (at the same level before block erase suspended) while block erase is suspended. rst# must remain at v ih and wp# must also remain at v il or v ih (at the same level before block erase suspended). block erase cannot resume until (page buffer) program operation initiated during block erase suspend is completed. figure 10 shows the block erase suspend and block erase resume flowchart. if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. rev. 2.44 fum00701 38 read array data read write d0h write ffh read array data sr.7= 0 1 sr.6= 0 1 done? no yes word/page buffer program read or write b0h, partition address read status register, partition address write 70h, partition address word/page buffer program loop word/page buffer program start completed block erase resumed block erase bus operation command comments write block erase suspend data=b0h addr=within partition write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.6 1=block erase suspended 0=block erase completed write block erase resume data=d0h addr=within block to be suspended figure 10. block erase suspend and block erase resume flowchart rev. 2.44 fum00701 39 4.12 (page buffer) program suspend command and (page buffer) program resume command the (page buffer) program suspend command (b0h) allows word and page buffer program interruption to read data from locations other than that which is suspended. once the (page buffer) program process starts in a partition, writing the (page buffer) program suspend command to the partition requests that the wsm suspends the (page buffer) program sequence at a predetermined point in the algorithm. read operations to the target partition after writing the (page buffer) program suspend command access the status register. status register bits sr.7 and sr.2 indicate if the (page buffer) program operation has been suspended (both will be set to "1"). specification t whrh1 or t ehrh1 defines the (page buffer) program suspend latency. when the (page buffer) program suspend command is written after the completion of the (page buffer) program operation, the partition returns to read array mode. therefore, the read status register command (70h) must be written to the target partition after writing the (page buffer) program suspend command. if the status register bits sr.7 and sr.2 are set to "1", (page buffer) program has been suspended. at this point, a read array command can be written to read data from locations other than that which is suspended. the valid commands while (page buffer) program is suspended are read array, read identifier codes/otp, read query, read status register and (page buffer) program resume command. the commands other than those mentioned above are not accepted and should not be used. for example, the block erase operation cannot be executed during a (page buffer) program suspend. to resume the (page buffer) program operation, write the (page buffer) program resume command (d0h) to the partition. status register bits sr.7 and sr.2 will be automatically cleared. after the (page buffer) program resume command is written, the target partition automatically outputs the status register data when read. v pp must remain at v pph1/2 (at the same level before (page buffer) program suspended) while (page buffer) program is suspended. rst# must remain at v ih and wp# must also remain at v il or v ih (at the same level before (page buffer) program suspended). figure 11 shows the (page buffer) program suspend and (page buffer) program resume flowchart. if the interval time from a (page buffer) program resume command to a subsequent (page buffer) program suspend command is short and its sequence is repeated, the (page buffer) program operation may not be finished. after the (page buffer) program suspend command is written to the 1st partition to suspend the program operation while the 2nd partition is in block erase suspend mode, the (page buffer) program resume command should be written to the 1st partition first to resume the suspended (page buffer) program operation. after that, the block erase resume command is written to the 2nd partition to resume the suspended block erase operation. if the block erase resume command is written before the (page buffer) program resume command, the block erase resume command is ignored and the partition to which the block erase resume command is written is set to read array mode with block erase suspended. rev. 2.44 fum00701 40 write d0h write ffh write ffh read array data read array data sr.7= 0 1 sr.2= 0 1 done? no yes read status register, partition address write b0h, partition address write 70h, partition address start program completed (page buffer) program resumed (page buffer) bus operation command comments write (page buffer) program suspend data=b0h addr=within partition write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.2 1=(page buffer) program suspended 0=(page buffer) program completed write data=ffh addr=within partition read read array locations from block other than that being programmed write (page buffer) program resume data=d0h addr=location to be suspended figure 11. (page buffer) program suspend and (page buffer) program resume flowchart rev. 2.44 fum00701 41 4.13 set block lock bit command the product is provided with a block lock bit for each parameter block and main block. the features of set block lock bit is as follows: any block can be independently locked by setting its block lock bit. the time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). block erase, full chip erase or (page buffer) program on a locked block cannot be executed (see table 11 and table 12). at power-up or device reset, all blocks default to locked state, regardless of the states before power-off or reset operation. (lock bit is volatile.) the set block lock bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be locked is written to the target partition. at the second cycle, command (01h) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock bit is set within the minimum command cycle time and the corresponding block is locked. to check the lock status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock/unlock status is represented by the output pin dq 0 . if the output of dq 0 is "1", the block lock bit is set correctly. figure 12 shows set block lock bit flowchart. the two-cycle command sequence ensures that block is not accidentally locked. an invalid set block lock bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the set block lock bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . at power-up or device reset, since all blocks default to locked state, write the clear block lock bit command described later to clear block lock bit before a erase or program operation. rev. 2.44 notes: 1. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 2. erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (wp#=0) or [101] (wp#=1), regardless of the states before power-off or reset operation. 4. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 5. otp (one time program) block has the lock function which is different from those described above. table 11. functions of block lock (5) and block lock-down current state erase/program allowed (2) state wp# dq 1 (1) dq 0 (1) state name [000] 0 0 0 unlocked yes [001] (3) 0 0 1 locked no [011] 0 1 1 locked-down no [100] 1 0 0 unlocked yes [101] (3) 1 0 1 locked no [110] (4) 1 1 0 lock-down disable yes [111] 1 1 1 lock-down disable no fum00701 42 notes: 1. "set lock" means set block lock bit command, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp# is not changed and fixed v il or v ih . notes: 1. "wp#=0 1" means that wp# is driven to v ih and "wp#=1 0" means that wp# is driven to v il . 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 12. block locking state transitions upon command write (4) current state result after lock command written (next state) state wp# dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000] 0 0 0 [001] no change [011] (2) [001] 0 0 1 no change (3) [000] [011] [011] 0 1 1 no change no change no change [100] 1 0 0 [101] no change [111] (2) [101] 1 0 1 no change [100] [111] [110] 1 1 0 [111] no change [111] (2) [111] 1 1 1 no change [110] no change table 13. block locking state transitions upon wp# transition (4) previous state current state result after wp# transition (next state) state wp# dq 1 dq 0 wp#=0 1 (1) wp#=1 0 (1) - [000] 0 0 0 [100] - - [001] 0 0 1 [101] - [110] (2) [011] 011 [110] - other than [110] (2) [111] - - [100] 1 0 0 - [000] - [101] 1 0 1 - [001] - [110] 110 - [011] (3) - [111] 1 1 1 - [011] rev. 2.44 fum00701 43 dq 0 /dq 1 = 0 1 write 90h, partition address write 60h, block address write 01h/2fh, block address read block address+2 bit complete set lock/lock-down sr.4,5= 1 0 read status register, partition address command sequence error start status check for all partitions if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions before set lock/lock-down operation for all partitions status check procedure exist? another partition yes no sr.7= 0 1 complete bus operation command comments write set block lock bit/set block lock- down bit fum00701 44 4.14 clear block lock bit command a locked block can be unlocked by writing the clear block lock bit command. the features of clear block lock bit is as follows: any block can be independently unlocked by clearing its block lock bit. the time required to be unlocked is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). block erase, full chip erase or (page buffer) program on an unlocked block can be executed (see table 11 and table 12). the clear block lock bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be unlocked is written to the target partition. at the second cycle, command (d0h) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock bit is cleared within the minimum command cycle time and the corresponding block is unlocked. to check the unlock status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock/unlock status is represented by the output pin dq 0 . if the output of dq 0 is "0", the block lock bit is cleared correctly. figure 13 shows clear block lock bit flowchart. the two-cycle command sequence ensures that block is not accidentally unlocked. an invalid clear block lock bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the clear block lock bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . 4.15 set block lock-down bit command the block lock-down bit, when set, increases the security for data protection. the block lock-down bit has the following functions. any block can be independently locked-down by setting its block lock-down bit. the time required to be locked-down is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). locked-down block is automatically locked regardless of wp# at v il or v ih . when wp# is v il , locked-down blocks are protected from lock status changes. when wp# is v ih , the lock-down bits are disabled and locked-down blocks can be individually unlocked by software command. these blocks can then be re-locked and unlocked as desired while wp# remains v ih . when wp# goes v il , blocks that were previously marked lock-down return to the locked and locked-down state regardless of any changes made while wp# was v ih (see table 13). at power-up or device reset, all blocks are not locked- down regardless of the states before power-off or reset operation. (lock-down bit is volatile.) lock-down bit cannot be cleared by software, only by power-off or device reset. the set block lock-down bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be locked-down is written to the target partition. at the second cycle, command (2fh) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock-down bit is set within the minimum command cycle time and the corresponding block is locked-down. to check the lock- down status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock-down status is represented by the output pin dq 1 . if the output of dq 1 is "1", the block lock-down bit is set correctly. figure 12 shows set block lock-down bit flowchart. rev. 2.44 fum00701 45 dq 0 = 1 0 write 90h, partition address write 60h, block address write d0h, block address read block address+2 complete clear lock bit sr.4,5= 1 0 read status register, partition address command sequence error start status check for all partitions if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions before clear lock operation for all partitions status check procedure exist? another partition yes no sr.7= 0 1 complete bus operation command comments write clear block lock bit fum00701 46 the two-cycle command sequence ensures that block is not accidentally locked-down. an invalid set block lock-down bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the set block lock-down bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . at power-up or device reset, since no blocks are locked- down, write the set block lock-down bit command as necessary. while wp# is v ih , the lock-down bits are disabled but not cleared. once any block is locked-down, it cannot be cleared until power-off or device reset. 4.16 otp program command otp program is executed by a two-cycle command sequence. at the first cycle, command (c0h) and an address within the otp block (see figure 4) is written, followed by the second write that specifies the address and data. after writing the command, the device outputs the status register data when any address within the device is selected. the wsm then takes over, controlling the internal otp program algorithm. the system cpu can detect the otp program completion by analyzing the output data of the status register bit sr.7. figure 14.1 and figure 14.2 show otp program flowchart. the address written at the command cycle must be the address within the otp block (refer to figure 4). writing an address outside the otp block will cause a otp program error and the status register bit sr.4 is set to "1". clear the status register before writing next command. the internal wsm verify only detects errors for "1"s that are not successfully programmed to "0"s. check the status register bit sr.4 at the end of otp program. if a otp program error is detected, the status register should be cleared before system software attempts corrective actions. for reliable otp program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, otp program operations are not guaranteed. for example, attempting an otp program at v pp v pplk causes sr.4 and sr.3 being set to "1". otp program operation on locked area causes sr.4 and sr.1 being set to "1" and the operation will not be executed. otp program cannot be suspended through the (page buffer) program suspend command (b0h). even if the (page buffer) program suspend command is written during otp program operation, the suspend command will be ignored. if an error is detected during the otp program operation, error bits for status registers in all partitions are set to "1". this requires that the clear status register command be written to all partitions to clear the error bits. dual work operation is not available while the otp program mode, and the memory array data cannot be read even if that operation has been completed. to return to the read array mode, write the read array command (ffh) to the partition ? s cui after the completion of the otp program operation. rev. 2.44 fum00701 47 sr.7= 0 1 start write data and address write c0h, otp address full status check if desired complete otp program status check for all partitions if desired set partition address to 1st partition write 70h, partition address read status register, partition address read status register set partition address to next partition status check for all partitions before otp program operation for all partitions status check procedure exist? another partition yes no sr.7= 0 1 complete bus operation command comments write otp program fum00701 48 read status register data full status check procedure sr.4= 1 0 otp program error sr.1= 1 0 device protect error sr.3= 1 0 v pp range error otp program successful bus operation command comments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect standby check sr.4 1=otp program error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 14.2. automated otp program flowchart (continued) rev. 2.44 fum00701 49 4.17 set partition configuration register command the partition configuration register (pcr) bits are set by writing the set partition configuration register command to the device. this operation is initiated by a two-cycle command sequence. the partition configuration register can be configured by writing the command with the partition configuration register code. at the first cycle, command (60h) and a partition configuration register code is written. at the second cycle, command (04h) and the same address as the first cycle is written. the partition configuration register code is placed on the address bus, a 15 - a 0 , and is latched on the rising edge of ce#, or we# (whichever occurs first). the partition configuration register code sets the partition boundaries. this command functions independently of the v pp voltage. rst# must be at v ih . after executing this command, the device returns to read array mode and status registers are cleared. figure 16 shows set partition configuration register flowchart. notes: the partition configuration register code can be read via the read identifier codes/otp command (90h). address 0006h on a 15 - a 0 contains the partition configuration register code (see table 6 through table 8). partition configuration after device power-up or reset is as follows. (partition configuration register bits are volatile.) plane 0-2 are merged into one partition. (top parameter device) plane1-3 are merged into one partition. (bottom parameter device) 4.17.1 how to set the partition configuration register the partition configuration register is set by writing the set partition configuration register command, as previously described. the following summarizes how to set the partition configuration register. at the first cycle of the set partition configuration register command, write the following data and address. data (command) dq 15 -dq 8 =any data. these bits do not affect the operation. dq 7 -dq 0 =60h address a 20 -a 16 =partition address (32m-bit device). a 21 -a 16 =partition address (64m-bit or 128m-bit device). the partition address must be the address within the partition in which the flash memory interface software is not stored. a 15 -a 11 =any address. these bits do not affect the operation. a 10 -a 8 =partition configuration register code. these bits determine the partiton boundaries shown in table 14 and figure 15. a 7 -a 0 =any address. these bits do not affect the operation. after writing the first cycle command (60h), the target partition to which the command is written is put into the read status register mode. subsequent read operations to that partition output the status register data of its partition. at the second cycle of the set partition configuration register command, write the following data and address. data (command) dq 15 -dq 8 =any data. these bits do not affect the operation. dq 7 -dq 0 =04h address (all addresses are the same as the first cycle.) a 20 -a 16 =partition address (32m-bit device). a 21 -a 16 =partition address (64m-bit or 128m-bit device). the partition address must be the address within the partition in which the flash memory interface software is not stored. rev. 2.44 fum00701 50 a 15 -a 11 =any address. these bits do not affect the operation. a 10 -a 8 =partition configuration register code. these bits determine the partiton boundaries shown in table 14 and figure 15. a 7 -a 0 =any address. these bits do not affect the operation. after writing the second cycle command (04h) and the operation is successfully completed, all the partitions return to the read array mode. if the operation is not completed successfully, the target partition to which the command is written remains in the read status register mode. after the second cycle command, write the read status register command (70h) to the partition to which the set partition configuration register command is written. then, check the status register of its partition to clarify that the command sequence error is not detected. if the command sequence error is detected (sr.5, sr.4="1"), write the clear status register command (50h) to the partition in which the error is detected. after that, reattempt the sequence of setting the partition configuration register. if the command sequence error is not detected, write the read identifier codes/otp command (90h) to the partition to which the set partition configuration register command is written. subsequent read operations at the following address output the partition configuration register code. a 20 -a 16 =partition address (32m-bit device). a 21 -a 16 =partition address (64m-bit or 128m-bit device). the partition address must be the address within the partition to which the read identifier codes/ otp command is written. a 15 -a 0 =0006h check the partition configuration register code on the data bus dq 10 -dq 8 to clarify that the partition boundaries are correctly set. if the partition boundaries are not set correctly, reattempt the sequence of setting the partition configuration register. 4.17.2 partition configuration the partition configuration shown in table 14 determines the partiton boundaries for the dual work (simultaneous read while erase/program) operation. the partition boundaries can be set to any plane boundaries. if the partition configuration register bits pcr.10-8 (pc.2-0) are set to "001", the partition boundary is set between plane0 and plane1. there are two partitions in this configuration. plane1-3 are merged to one partition. status registers for plane1-3 are also merged to one. if the partition configuration register bits are set to "101", the partition boundaries are set between plane0 and plane1 and between plane2 and plane3. there are three partitions in this configuration. plane1-2 are merged to one partition. if the partition configuration register bits are set to "111", there are four partitions. figure 15 illustrates the various partition configuration. rev. 2.44 fum00701 51 table 14. partition configuration register definition rrrrrpc2pc1pc0 15 14 13 12 11 10 9 8 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0-1 and plane2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in a top parameter device) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respectively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: after power-up or device reset, pcr10-8 (pc2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. see figure 15 for the detail on partition configuration. pcr.15-11 and pcr.7-0 are reserved for future use and should be masked out when checking the partition configuration register. plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 plane1 plane0 plane2 plane3 partition1 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 plane1 plane0 plane2 plane3 partition0 partition1 partition1 partition0 partition2 partition3 partition2 partition2 partition1 partition2 000 001 010 100 011 110 101 111 pc2 pc1pc0 partitioning for dual work partitioning for dual work pc2 pc1pc0 rev. 2.44 figure 15. partition configuration fum00701 52 set correctly? no yes write 90h, partition address write 60h, configuration register code write 04h, configuration register code read a 15 - a 0 =0006h register complete set partition configuration sr.4,5= 1 0 read status register, partition address command sequence error start status check for all partitions if desired set partition address to 1st partition write 70h, partition address read status register, partition address set partition address to next partition status check for all partitions configuration register operation before set partition status check procedure exist? another partition yes no sr.7= 0 1 complete write 70h, partition address for all partitions bus operation command comments write set partition configuration register fum00701 53 5 design considerations 5.1 hardware design considerations 5.1.1 control using rst#, ce# and oe# the device will often be used in large memory arrays. sharp provides three control input pins to accommodate multiple memory connection. three control input pins, rst#, ce# and oe# provide for: minimize the power consumption of the memory avoid data confliction on the data bus to effectively use these control input pins, access the desired memory by enabling the ce# through the address decoder. connect oe# to read# control signal of all memory devices and system. with these connections, the selected memory devices are activated and deselected memory devices are in standby mode. rst# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should toggle (once set to v il ) during system reset. 5.1.2 power supply decoupling flash memory ? s power switching characteristics require careful device decoupling for eliminating noises to the system power lines. system designers should consider standby current levels (i ccs ), active current levels (i ccr ) and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs ? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc , v ccq and gnd and between v pp and gnd (when v pp is used as 12v supply). these high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the array ? s power supply connection between v cc and gnd. these capacitors will overcome voltage slumps caused by circuit board trace inductance. 5.1.3 v pp traces on printed circuit boards the v pp pin on the product is only used to monitor the power supply voltage and is not used for a power supply pin except for 12v supply. therefore, even when on- board writing to the flash memory on the system, it is not required to consider that v pp supplies the currents on the printed circuit boards. however, in erase or program operations with applying 12v0.3v to v pp pin, v pp is used for the power supply pin. when executing these operations, v pp trace widths and layout should be similar to that of v cc to supply the flash memory cells current for erasing or programming. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 5.1.4 v cc , v pp , rst# transitions if v pp is lower than v pplk , v cc is lower than v lko , or rst# is not at v ih , block erase, full chip erase, (page buffer) program and otp program operation are not guaranteed. when v pp error is detected, the status register bits sr.5 or sr.4 (depending on the attempted operation) and sr.3 will be set to "1". if rst# transitions to v il during the block erase, full chip erase, (page buffer) program or otp program operation, the status register bit sr.7 will remain "0" until reset operation has been completed. then, the attempted operation will be aborted and the device will enter reset mode after the completion of the reset sequence. if rst# is taken v il during a block erase, full chip erase, (page buffer) program or otp program operation, the memory contents at the aborted location are no longer valid. therefore, the proper command must be written again after rst# is driven v ih . and also, if v cc transitions to lower than v lko during a block erase, full chip erase, (page buffer) program or otp program operation, the attempted operation will be aborted and the memory contents at the aborted location are no longer valid. write the proper command again after v cc transitions above v lko . rev. 2.44 fum00701 54 5.1.5 power-up/down protection the product is designed to offer protection against accidental block erase, full chip erase, (page buffer) program, otp program due to noises during power transitions. when the device power-up, holding v pp and rst# to gnd until v cc has reached the specified level and in stable. for additional information, please refer to the ap-007-sw-e rst#, v pp electric potential switching circuit . after power-up, the product defaults to the mode described in section 2.1. system designers must guard against spurious writes when v cc voltages are above v lko and v pp voltages are above v pplk , by referring to section 5.3 and the following design considerations. since both ce# and we# must be at v il for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection because alternation of memory contents can only occur after successful completion of the two-step command sequences. the individual block locking scheme, which enables each block to be independently locked, unlocked or locked- down, prevents the accidental data alternation. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus conditions can be masked, providing yet another level of memory protection. 5.1.6 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. the nonvolatility of the product increases usable battery life because data is retained when system power is removed. 5.1.7 automatic power savings automatic power savings (aps) provides low-power operation during active mode. aps mode allows the flash memory to put itself into a low current state when not being accessed. after data is read from the memory array and addresses not switching, the device enters the aps mode where typical i cc current is comparable to i ccs . the flash memory stays in this static state with outputs valid until a new location is read. standard address access timings (t avqv ) provide new data when addresses are changed. during dual work operation (one partition being erased or programmed, while other partitions are one of read modes), the device cannot enter the aps mode even if the input address remains unchanged. 5.1.8 reset operation during power-up/down or transitions of power supply voltage, hold the rst# pin at v il to protect data against noises which are caused by invalid bus conditions and initialize the internal circuitry in flash memory. bringing rst# to v il resets the internal wsm (write state machine) and sets the status register to 80h. after return from reset, a time t phqv is required until outputs are valid, and a delay, t phwl and t phel , is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. rev. 2.44 fum00701 55 5.2 software design considerations 5.2.1 wsm (write state machine) polling the status register bit sr.7 provides a software method of detecting block erase, full chip erase, (page buffer) program and otp program completion. after the block erase, full chip erase, (page buffer) program or otp program command is written to the cui (command user interface), sr.7 goes to "0". it will return to "1" when the wsm (write state machine) has completed the internal algorithm. the status register bit sr.7 is "1" state when the device is in the following mode. the device can accept the next command. block erase is suspended and (page buffer) program operation is not executed. (page buffer) program is suspended. reset mode 5.2.2 attention to program operation do not re- program "0" data for the bit in which "0" has been already programmed. this re- program operation may generate the bit which cannot be erased. to change the data from "1" to "0", take the following steps. program "0" for the bit in which you want to change the data from "1" to "0". program "1" for the bit in which "0" has been already programmed. (when "1" is programmed, erase/program operations are not executed onto the memory cell in flash memory.) for example, changing the data from "10111101" to "10111100" requires "11111110" programmed. 5.3 data protection method noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands and causes undesired memory updating. to protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: ? the below describes data protection method. 1) protection of data in each block ny locked block by setting its block lock bit is protected against the data alternation. when wp# is v il , any locked-down block by setting its block lock- down bit is protected from lock status changes. by using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). for detailed block locking scheme, refer to sections 4.13 to 4.15. 2) protection of data with v pp control when the level of v pp is lower than v pplk (v pp lockout voltage), write functions to all blocks including otp block are disabled. all blocks are locked and the data in the blocks are completely protected. 3) protection of data with rst# especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing rst# to v il , which inhibits write operation to all blocks including otp block. for detailed description on rst# control, refer to section 5.1.5. ? protection against noises on we# signal to prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on we# signal. rev. 2.44 fum00701 56 5.4 high performance read mode this section describes the high performance read mode to increase the read performance. however, the read mode which is available varies according to each product. refer to the specifications whether the high performance read mode is available or not. the read mode which is not described in the specifications can not be used for that product, even if that read mode is explained in this section. 5.4.1 cpu compatibility the product supports high-performance read mode for the parameter and main blocks: asynchronous read mode in which 8-word page mode is available this read mode provides much higher read accesses than was previously used. the asynchronous read mode is suitable for non-clocked memory systems and is compatible with standard page- mode rom. if the system cpu or asic does not support page-mode, single asynchronous read modes can be used. upon reset, the device defaults to asynchronous read mode and is put into read array mode. 5.4.2 using asynchronous page mode after initial power-up or reset mode, the device defaults to asynchronous read mode in which 8-word page mode is available. the asynchronous page mode is available for the parameter and main blocks, and is not supported from other locations within the device, such as the status register, identifier codes, otp block and query codes. the initial valid address will store 8 words of data in the internal page buffer. each word is then output onto the data bus by toggling the address a 2-0 . the addresses cannot be latched into the device. therefore, addresses must stay valid throughout the entire read cycle until ce# goes to v ih . figure 17.1 and figure 17.2 show a waveform for asynchronous page mode read timing. note that the address a 2-0 must be toggled to output the page-mode data. 5.4.3 single read mode the following data can only be read in single asynchronous read mode. status register query code manufacturer code device code block lock configuration code partition configuration register code otp block a waveform of read timing for single asynchronous read mode is shown in figure 18. single asynchronous read mode is compatible with previous sharp flash memory devices. the valid addresses are asserted, and then the device will output data after certain delay time, such as t avqv , t vlqv , t elqv or t glqv . addresses must stay valid throughout the entire read cycle until ce# goes to v ih . rev. 2.44 fum00701 57 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv high z v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (w) (g) (e) (a) a 20-3 v ih v il (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address valid address valid address valid address valid output valid output valid output valid output valid address t avav a 21-3 (a) figure 17.1. ac waveform for asynchronous 4-word page mode read operations from main blocks or parameter blocks (a 21 is not used for 32m-bit device.) rev. 2.44 fum00701 58 rev. 2.44 figure 17.2. ac waveform for asynchronous 8-word page mode read operations from main blocks or parameter blocks (a 21 is not used for 32m-bit device.) t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv v ih v il v ih v il v ih v il v ih v il v ih v il (p) (w) (g) (e) (a) a 20-3 (a) a 2-0 (d/q) dq 15-0 ce# oe# we# rst# t glqx t elqx valid address t avav v ih v il valid address valid address valid address valid address high z v oh v ol valid output valid output valid output valid output valid address valid address valid address valid address valid output valid output valid output valid output a 21-3 (a) fum00701 59 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 20-0 dq 15-0 ce# oe# we# rst# high z t elqx valid output valid address t avav t glqx t ghgl t ehel t avel t avgl t glax t elax t oh a 21-0 (a) figure 18. ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code (a 21 is not used for 32m-bit device.) rev. 2.44 fum00701 60 6 common flash interface this section defines the data structure of the common flash interface (cfi) code, which is called query code. query code can be read by writing the read query command (98h) to the target partition ? s cui. system software should confirm this code to gain critical information such as block size, density, bit organization and electrical specifications. once this code has been obtained, the software will understand which command sets should be used to enable erases, programs and other operations for the flash memory device. the query code is part of an overall specification for multiple command set and control interface descriptions called common flash interface or cfi. 6.1 query structure output the query code allows system software to obtain how to control the flash memory device. the following describes the cfi-compliant interface that allows access to the query code. . the numerical offset value is the address relative to the maximum bus width supported by the device. the query table device starting address is a 10h, which is a word address for 16 devices. the query code is presented on the lower-byte data outputs (dq 7-0 ). the device outputs "00h" data on upper byte (dq 15-8 ) in the read query mode. when verifying the query code information, the upper byte data should be ignored. when the query addresses contain two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, even if the "h" suffix is not noted. some query code data vary according to the device types. refer to the specifications for the device type to which the product correspond. in the case of the product which has two or more be# (ce#) pins , refer to the query code information of "device type" which indicates the same density value as the memory density selected by each be# (ce#) pin. in the case of the product which has 32-bit i/o interface, the query code information of "device type" which indicates the value of half a memory density is presented on both lower-word (dq 15-0 ) and upper-word (dq 31-16 ) data outputs. example of query structure output is shown below. offset: address a 7 -a 0 for reading the query code. a 7 -a 0 =offset value shown in the table. a 15 -a 8 =these bits do not affect the operation. a 20 -a 16 =partition address (32m-bit device) a 21 -a 16 =partition address (64m-bit or 128m-bit device) the partition address must be the address within the partition to which the read query command (98h) is written. length: address length of query code. each query code information is represented at the addresses from "offset" to "offset+length ? 1". description: explanation of each query code. data: query code data. "10: 0051h" means that the read operation at the address a 7 -a 0 ="10h" outputs the data dq 15 -dq 0 ="0051h". value: meaning of the output data. table 15. example of query structure output offset length description data value 10h 3 query-unique ascii string "qry" 10: 0051h q 11: 0052h r 12: 0059h y rev. 2.44 fum00701 61 6.2 query structure overview the below table summarized the query structure, which contains the address locations (offset), the section name and the information for each query code. note: 1. ba = the beginning location of a block address. 6.3 block status register the block status register indicates whether a target block is locked or locked-down. block erase, full chip erase or (page buffer) program on the locked block cannot be executed. the block status register is accessed from block base address (t he beginning location of a block address ) +2. note: 1. ba = the beginning location of a block address. table 16. query structure offset section name information 00h manufacturer code (refer to table 6 through table 8) 01h device code (refer to table 6 through table 8) (ba+2)h (1) block status register block lock/lock-down information 03h-0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device voltage and timing information 27h device geometry definition flash device layout information 39h sharp-specific extended query table vendor-defined additional information specific to the primary vendor algorithm table 17. block status register offset length description data value (ba+2)h (1) 1 block status register bit 0 block lock status 0 = unlocked 1 = locked bit 1 block lock-down status 0 = not locked-down 1 = locked-down bit 2-bit 7 reserved for future use (ba+2): bit 0=0 or 1 bit 1=0 or 1 see "description" rev. 2.44 fum00701 62 6.4 cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates that the specification version and supported vendor-specified command set(s). table 18. cfi query identification string offset length description data value 10h 3 query-unique ascii string "qry" 10: 0051h q 11: 0052h r 12: 0059h y 13h 2 primary vendor command set and control interface id code 16-bit id code for vendor-specified algorithms 13: 0003h 14: 0000h 15h 2 extended query table primary algorithm address 15: 0039h 16: 0000h 39h 17h 2 alternate vendor command set and control interface id code 0000h means no second vendor-specified algorithm exists 17: 0000h 18: 0000h n/a 19h 2 secondary algorithm extended query table address 0000h means none exists 19: 0000h 1a: 0000h n/a rev. 2.44 fum00701 63 6.5 system interface information the following system interface information is useful for optimizing the system interface to the flash memory. note: 1. the query code data varies according to each device type. flash memory: flash memory device. combination memory: flash memory and sram into one package. other than 44sop: the products other than that which is available in 44-lead sop package. 44sop: the product which is available in 44-lead sop package. 32mbit: 32m-bit device. 64mbit: 64m-bit device. table 19. system interface information offset length description device type (1) data value 1bh 1 vcc logic supply minimum program/erase voltage bits 0-3 bcd 100mv bits 4-7 bcd volts 1b: 0027h 2.7v 1ch 1 vcc logic supply maximum program/erase voltage bits 0-3 bcd 100mv bits 4-7 bcd volts flash memory 1c: 0036h 3.6v combination memory 1c: 0033h 3.3v 1dh 1 vpp [programming] supply minimum program/erase voltage bits 0-3 bcd 100mv bits 4-7 hex volts other than 44sop 1d: 00b7h 11.7v 44sop 1d: 0000h vpp pin not provided. 1eh 1 vpp [programming] supply maximum program/erase voltage bits 0-3 bcd 100mv bits 4-7 hex volts other than 44sop 1e: 00c3h 12.3v 44sop 1e: 0000h vpp pin not provided. 1fh 1 "n" such that typical single word program time-out = 2 n s 1f: 0004h 2 4 =16 s 20h 1 "n" such that typical max. size buffer write time-out = 2 n s 20: 0007h 2 7 =128 s 21h 1 "n" such that typical block erase time-out = 2 n ms 21: 000ah 2 10 =1s 22h 1 "n" such that typical full chip erase time-out = 2 n ms 32mbit 22: 0010h 2 16 = 65.5s 64mbit 22: 0011h 2 17 = 131s 23h 1 "n" such that maximum word program time-out = 2 n times typical 23: 0004h 2 4 16 s= 256 s 24h 1 "n" such that maximum max. size buffer write time-out = 2 n times typical 24: 0004h 2 4 128 s= 2048 s 25h 1 "n" such that maximum block erase time-out = 2 n times typical 25: 0003h 2 3 1s= 8s 26h 1 "n" such that maximum full chip erase time-out = 2 n times typical 32mbit 26: 0003h 2 3 65.5s= 524s 64mbit 26: 0003h 2 3 131s= 1048s rev. 2.44 fum00701 64 6.6 device geometry definition this section provides the critical details of the flash device geometry. note: 1. the query code data varies according to each device type. 32mbit: 32m-bit device. 64mbit: 64m-bit device. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. table 20.1. device geometry definition offset length description device type (1) data value 27h 1 "n" such that device size = 2 n in number of bytes 32mbit 27: 0016h 32mbit 64mbit 27: 0017h 64mbit 28h 2 flash device interface 8: 8-bit data bus (--00h) 16: 16-bit data bus (0001h) 8/ 16: 8-bit/16-bit data bus (0002h) 28: 0001h 29: 0000h 16 2ah 2 "n" such that maximum number of bytes in write buffer = 2 n 2a: 0005h 2b: 0000h 16word 2ch 1 number of erase block regions within device 1. x = 0 means no erase blocking; the device erases in "bulk". 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region. 4. partition size = (total blocks) (individual block size) 2c: 0002h 2 2dh 4 erase block region 1 information bits 0-15 = y, y+1 = number of identical-size erase blocks bit 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter 2d: 003eh 2e: 0000h 2f: 0000h 30: 0001h 63blocks 32kwords 32mbit, bottom parameter 2d: 0007h 2e: 0000h 2f: 0020h 30: 0000h 8blocks 4kwords 64mbit, top parameter 2d: 007eh 2e: 0000h 2f: 0000h 30: 0001h 127blocks 32kwords 64mbit, bottom parameter 2d: 0007h 2e: 0000h 2f: 0020h 30: 0000h 8blocks 4kwords rev. 2.44 fum00701 65 note: 1. the query code data varies according to each device type. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. table 20.2. device geometry definition (continued) offset length description device type (1) data value 31h 4 erase block region 2 information bit 0-15 = y, y+1 = number of identical-size erase blocks bit 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter 31: 0007h 32: 0000h 33: 0020h 34: 0000h 8blocks 4kwords 32mbit, bottom parameter 31: 003eh 32: 0000h 33: 0000h 34: 0001h 63blocks 32kwords 64mbit, top parameter 31: 0007h 32: 0000h 33: 0020h 34: 0000h 8blocks 4kwords 64mbit, bottom parameter 31: 007eh 32: 0000h 33: 0000h 34: 0001h 127blocks 32kwords 35h 4 erase block region 3 information bit 0-15 = y; y+1 = number of identical-size erase blocks bit 16-31 = z; region erase block(s) size are z 256 bytes 35: 0000h 36: 0000h 37: 0000h 38: 0000h n/a rev. 2.44 fum00701 66 6.7 sharp-specific extended query table the vendor-specific extended query tables show the features and commands which are supported in the product. table 21. primary vendor-specific extended query offset length description data value 39h 3 primary extended query table unique ascii string "pri" 39: 0050h p 3a: 0052h r 3b: 0049h i 3ch 1 major version number, ascii 3c: 0031h 1 3dh 1 minor version number, ascii 3d: 0033h 3 rev. 2.44 fum00701 67 note: 1. the query code data varies according to each device type. page mode: the device which supports page mode read operations. single fixed partition: the device which does not support the flexible partition configuration. (for example, the product which is available in 44-lead sop package.) single partition contains all the blocks. the partition configuration cannot be chang ed. table 22.1. primary algorithm-specific extended query offset length description device type (1) data value 3eh 4 optional feature and command support (1 = yes, 0 = no) bits 10-31 are reserved; undefined bits are "0." if bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 chip erase supported bit 1 suspend erase supported bit 2 suspend program supported bit 3 legacy lock/unlock supported bit 4 queued erase supported bit 5 instant individual block locking supported bit 6 otp bits supported bit 7 page mode read supported bit 8 synchronous read supported bit 9 simultaneous operations supported page mode 3e: 00e7h 3f: 0002h 40: 0000h 41: 0000h bit 0=1 yes bit 1=1 yes bit 2=1 yes bit 3=0 no bit 4=0 no bit 5=1 yes bit 6=1 yes bit 7=1 yes bit 8=0 no bit 9=1 yes single fixed partition 3e: 00e7h 3f: 0000h 40: 0000h 41: 0000h bit 0=1 yes bit 1=1 yes bit 2=1 yes bit 3=0 no bit 4=0 no bit 5=1 yes bit 6=1 yes bit 7=1 yes bit 8=0 no bit 9=0 no rev. 2.44 fum00701 68 note: 1. the query code data varies according to each device type. v pp =v pph1 /v pph2 : the device which supports the fast erasing and fast programming mode with applying 12v to v pp . v pp =v pph1 : the device which does not support the fast erasing and fast programming mode. 44sop: the product which is available in 44-lead sop package. table 22.2. primary algorithm-specific extended query (continued) offset length description device type (1) data value 42h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1-7 are reserved; undefined bits are "0" bit 0 program supported after erase suspend 42: 0001h bit 0=1 yes 43h 2 block status register mask bit 2-15 are reserved; undefined bits are "0" bit 0 block lock bit status register active bit 1 block lock-down bit status active 43: 0003h 44: 0000h bit 0=1 yes bit 1=1 yes 45h 1 vcc logic supply highest performance program/erase voltage bit 0-3 bcd value in 100mv bit 4-7 bcd value in volts 45: 0030h 3.0v 46h 1 vpp optimum program/erase supply voltage bits 0-3 bcd value in 100mv bits 4-7 hex value in volts v pp =v pph1 / v pph2 46: 00c0h 12.0v v pp =v pph1 46: 0030h 3.0v 44sop 46: 0000h vpp pin not provided. table 23. otp block information offset length description data value 47h 1 number of otp block fields in jedec id space "00h" indicates that 256 protection fields are available 47: 0001h 1 48h 4 otp block field 1: otp description this field describes user-available one time programmable (otp) block bytes. some are pre-programmed with device-unique numbers. others are user-programmable. bits 0-15 point to the otp block lock byte, the section ? s first byte. the following bytes are factory pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = "n" such that 2 n = factory pre-programmed bytes bits 24-31 = "n" such that 2 n = user-programmable bytes 48: 0080h 49: 0000h 4a: 0003h 4b: 0003h 80h 00h 8byte 8byte rev. 2.44 fum00701 69 note: 1. the query code data varies according to each device type. page mode: the device which supports page mode read operations. table 24. burst read information offset length description device type (1) data value 4ch 1 page mode read capability bits 0-7 = "n" such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine the page-mode data output width. 00h indicates no read page buffer. 4c: 0004h 8word 4dh 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. page mode 4d: 0000h no 4eh 1 synchronous mode read capability configuration 1 bits 3-7 are reserved; bits 0-2 "n" such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device ? s burstable address space. this field ? s 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. page mode 4e: 0000h n/a 4fh 1 synchronous mode read capability configuration 2 page mode 4f: 0000h n/a 50h 1 synchronous mode read capability configuration 3 page mode 50: 0000h n/a rev. 2.44 fum00701 70 notes: 1. the query code data varies according to each device type. flexible partition: the device which supports the flexible partition configuration. the partition boundaries can be changed by using the set partition configuration register command. two fixed partitions: the device which does not support the flexible partition configuration. the memory array is divided into two partitions and the partition configuration cannot be changed. refer to the specification for the partition boundary. single fixed partition: the device which does not support the flexible partition configuration. (for example, the product which is available in 44-lead sop package.) single partition contains all the blocks. the partition configuration cannot be chang ed. 2. this is the default value after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect this value. for example, even if the memory array is divided into four partitions by using the set partition configuration register command, the query code data at the offset "51h" remains "0002h". 3. if the query code data at the offset "51h" is "0000h", subsequent query code data from the offset "52h" to "77h" are all "ffffh". table 25. partition information offset length description device type (1) data value 51h 1 number of device hardware-partition regions within the device x = 0: a single hardware partition device (no fields follow) x specifies the number of device partition regions containing one or more contiguous erase block regions (flexible) flexible partition 51: 0002h 2 (2) two fixed partitions 51: 0002h 2 single fixed partition 51: 0000h 0 (3) rev. 2.44 fum00701 71 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. 2. the query code data varies according to each device type. top parameter: the device which contains the parameter blocks at the highest address. bottom parameter: the device which contains the parameter blocks at the lowest address. 3. simultaneous program and erase is not allowed. table 26.1. partition region 1 information (partition and erase-block region information) (1) offset length description device type (2) data value 52h 2 number of identical partitions within the partition region 52: 0001h 53: 0000h 1 54h 1 simultaneous program or erase operations allowed in other partitions while this partition is in read mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 54: 0011h program: 1 erase: 1 (3) 55h 1 simultaneous program or erase operations allowed in other partitions while this partition is in program mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 55: 0000h program: 0 erase: 0 56h 1 simultaneous program or erase operations allowed in other partitions while this partition is in erase mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 56: 0000h program: 0 erase: 0 57h 1 number of erase block regions in this partition region 1. x = 0 = no erase blocking; the partition region erases in "bulk" 2. x specifies the number of erase block regions containing one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) (individual block size) top parameter 57: 0001h 1 bottom parameter 57: 0002h 2 rev. 2.44 fum00701 72 rev. 2.44 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. for example, after the memory array of 32m-bit device is divided into four partitions by using the set partition configuration register command, the number of 32k-word blocks in one partition are 15 or 16 blocks. however, the query code data at the offset "58h" remains unchanged. 2. the query code data varies according to each device type. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. page mode: the device which supports page mode read operations. table 26.2. partition region 1 information (partition and erase-block region information) (1) (continued) offset length description device type (2) data value 58h 4 partition region 1 erase block region 1 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter 58: 002fh 59: 0000h 5a: 0000h 5b: 0001h 48blocks 32kwords 32mbit, bottom parameter 58: 0007h 59: 0000h 5a: 0020h 5b: 0000h 8blocks 4kwords 64mbit, top parameter 58: 005fh 59: 0000h 5a: 0000h 5b: 0001h 96blocks 32kwords 64mbit, bottom parameter 58: 0007h 59: 0000h 5a: 0020h 5b: 0000h 8blocks 4kwords 5ch 2 partition region 1 (erase block region 1) minimum block erase cycles 1000 5c: 0064h 5d: 0000h 100,000 cycles 5eh 1 partition region 1 (erase block region 1) bits per cell; internal error correction (ecc) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ecc used" (1 = yes, 0 = no) bits 5-7 = reserved for future use 5e: 0001h 1bit/cell bit 4=0 no 5fh 1 partition region 1 (erase block region 1) page mode and synchronous mode capabilities as defined in "burst read information" bit 0 = page mode host reads permitted (1 = yes, 0 = no) bit 1 = synchronous host reads permitted (1 = yes, 0 = no) bit 2 = synchronous host writes permitted (1 = yes, 0 = no) bits 3-7 = reserved for future use page mode 5f: 0001h bit 0=1 yes bit 1=0 no bit 2=0 no rev. 2.44 fum00701 73 rev. 2.44 rev. 2.44 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. for example, after the memory array of 32m-bit device is divided into two partitions in which each partition has 16m-bit density by using the set partition configuration register command, the number of 32k-word blocks in each partition are 31 or 32 blocks. however, the query code data at the offset "60h" remains unchanged. 2. the notation (bottom) in "offset" means that offset addresses are applicable to only bottom parameter device. refer to "partition region 2 information" for offset addresses from "60h" to "67h" of the top parameter device. 3. the query code data varies according to each device type. top parameter: the device which contains the parameter blocks at the highest address. bottom parameter: the device which contains the parameter blocks at the lowest address. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. table 26.3. partition region 1 information (partition and erase-block region information) (1) (continued) offset (2) length description device type (3) data value 60h (bottom) 4 (information for bottom parameter device) partition region 1 erase block region 2 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter n/a n/a 32mbit, bottom parameter 60: 000eh 61: 0000h 62: 0000h 63: 0001h 15blocks 32kwords 64mbit, top parameter n/a n/a 64mbit, bottom parameter 60: 001eh 61: 0000h 62: 0000h 63: 0001h 31blocks 32kwords 64h (bottom) 2 (information for bottom parameter device) partition region 1 (erase block region 2) minimum block erase cycles 1000 top parameter n/a n/a bottom parameter 64: 0064h 65: 0000h 100,000 cycles 66h (bottom) 1 (information for bottom parameter device) partition region 1 (erase block region 2) bits per cell; internal error correction (ecc) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ecc used" (1 = yes, 0 = no) bits 5-7 = reserved for future use top parameter n/a n/a bottom parameter 66: 0001h 1bit/cell bit 4=0 no 67h (bottom) 1 (information for bottom parameter device) partition region 1 (erase block region 2) page mode and synchronous mode capabilities defined in "burst read information" bit 0 = page mode host reads permitted (1 = yes, 0 = no) bit 1 = synchronous host reads permitted (1 = yes, 0 = no) bit 2 = synchronous host writes permitted (1 = yes, 0 = no) bits 3-7 = reserved for future use page mode, top parameter n/a n/a page mode, bottom parameter 67: 0001h bit 0=1 yes bit 1=0 no bit 2=0 no rev. 2.44 fum00701 74 page mode, top parameter: the device which supports page mode read operations and contains the parameter blocks at the highest address. page mode, bottom parameter: the device which supports page mode read operations and contains the parameter blocks at the lowest address. rev. 2.44 fum00701 75 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. 2. the notation (top) in "offset" means that offset addresses are applicable to top parameter device. the notation (bottom) in "offset" means that offset addresses are applicable to bottom parameter device. 3. the query code data varies according to each device type. top parameter: the device which contains the parameter blocks at the highest address. bottom parameter: the device which contains the parameter blocks at the lowest address. 4. simultaneous program and erase is not allowed. table 27.1. partition region 2 information (partition and erase-block region information) (1) offset (2) length description device type (3) data value 60h (top) 2 number of identical partitions within the partition region 60: 0001h 61: 0000h 1 68h (bottom) 68: 0001h 69: 0000h 62h (top) 1 simultaneous program or erase operations allowed in other partitions while this partition is in read mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 62: 0011h program: 1 erase: 1 (4) 6ah (bottom) 6a: 0011h 63h (top) 1 simultaneous program or erase operations allowed in other partitions while this partition is in program mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 63: 0000h program: 0 erase: 0 6bh (bottom) 6b: 0000h 64h (top) 1 simultaneous program or erase operations allowed in other partitions while this partition is in erase mode bits 0-3 = number of simultaneous program operations bits 4-7 = number of simultaneous erase operations 64: 0000h program: 0 erase: 0 6ch (bottom) 6c: 0000h 65h (top) 1 number of erase block regions in this partition region 1. x = 0 = no erase blocking; the partition region erases in "bulk" 2. x specifies the number of erase block regions containing one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) (individual block size) top parameter 65: 0002h 2 6dh (bottom) bottom parameter 6d: 0001h 1 rev. 2.44 fum00701 76 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. for example, after the memory array of 32m-bit device is divided into two partitions in which each partition has 16m-bit density by using the set partition configuration register command, the number of 32k-word blocks in each partition are 31 or 32 blocks. however, the query code data at the offset "66h" remains unchanged. 2. the notation (top) in "offset" means that offset addresses are applicable to top parameter device. the notation (bottom) in "offset" means that offset addresses are applicable to bottom parameter device. 3. the query code data varies according to each device type. top parameter: the device which contains the parameter blocks at the highest address. bottom parameter: the device which contains the parameter blocks at the lowest address. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. table 27.2. partition region 2 information (partition and erase-block region information) (1) (continued) offset (2) length description device type (3) data value 66h (top) 4 partition region 2 erase block region 1 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter 66: 000eh 67: 0000h 68: 0000h 69: 0001h 15blocks 32kwords 6eh (bottom) 32mbit, bottom parameter 6e: 002fh 6f: 0000h 70: 0000h 71: 0001h 48blocks 32kwords 66h (top) 64mbit, top parameter 66: 001eh 67: 0000h 68: 0000h 69: 0001h 31blocks 32kwords 6eh (bottom) 64mbit, bottom parameter 6e: 005fh 6f: 0000h 70: 0000h 71: 0001h 96blocks 32kwords 6ah (top) 2 partition region 2 (erase block region 1) minimum block erase cycles 1000 top parameter 6a: 0064h 6b: 0000h 100,000 cycles 72h (bottom) bottom parameter 72: 0064h 73: 0000h 100,000 cycles 6ch (top) 1 partition region 2 (erase block region 1) bits per cell; internal error correction (ecc) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ecc used" (1 = yes, 0 = no) bits 5-7 = reserved for future use top parameter 6c: 0001h 1bit/cell bit 4=0 no 74h (bottom) bottom parameter 74: 0001h 1bit/cell bit 4=0 no 6dh (top) 1 partition region 2 (erase block region 1) page mode and synchronous mode capabilities as defined in "burst read information" bit 0 = page mode host reads permitted (1 = yes, 0 = no) bit 1 = synchronous host reads permitted (1 = yes, 0 = no) bit 2 = synchronous host writes permitted (1 = yes, 0 = no) bits 3-7 = reserved for future use page mode, top parameter 6d: 0001h bit 0=1 yes bit 1=0 no bit 2=0 no 75h (bottom) page mode, bottom parameter 75: 0001h bit 0=1 yes bit 1=0 no bit 2=0 no rev. 2.44 fum00701 77 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. page mode, top parameter: the device which supports page mode read operations and contains the parameter blocks at the highest address. page mode, bottom parameter: the device which supports page mode read operations and contains the parameter blocks at the lowest address. rev. 2.44 fum00701 78 notes: 1. this table shows the default informations after power-up or device reset and until changing the partition configuration. changes of the partition configuration do not affect the query code data shown above. 2. the notation (top) in "offset" means that offset addresses are applicable to only top parameter device. refer to previous page for offset addresses from "6eh" to "75h" of the bottom parameter device. 3. the query code data varies according to each device type. top parameter: the device which contains the parameter blocks at the highest address. bottom parameter: the device which contains the parameter blocks at the lowest address. 32mbit, top parameter: 32m-bit device which contains the parameter blocks at the highest address. 32mbit, bottom parameter: 32m-bit device which contains the parameter blocks at the lowest address. 64mbit, top parameter: 64m-bit device which contains the parameter blocks at the highest address. 64mbit, bottom parameter: 64m-bit device which contains the parameter blocks at the lowest address. table 27.3. partition region 2 information (partition and erase-block region information) (1) (continued) offset (2) length description device type (3) data value 6eh (top) 4 (information for top parameter device) partition region 2 erase block region 2 information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z 256 bytes 32mbit, top parameter 6e: 0007h 6f: 0000h 70: 0020h 71: 0000h 8blocks 4kwords 32mbit, bottom parameter n/a n/a 64mbit, top parameter 6e: 0007h 6f: 0000h 70: 0020h 71: 0000h 8blocks 4kwords 64mbit, bottom parameter n/a n/a 72h (top) 2 (information for top parameter device) partition region 2 (erase block region 2) minimum block erase cycles 1000 top parameter 72: 0064h 73: 0000h 100,000 cycles bottom parameter n/a n/a 74h (top) 1 (information for top parameter device) partition region 2 (erase block region 2) bits per cell; internal error correction (ecc) bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ecc used" (1 = yes, 0 = no) bits 5-7 = reserved for future use top parameter 74: 0001h 1bit/cell bit 4=0 no bottom parameter n/a n/a 75h (top) 1 (information for top parameter device) partition region 2 (erase block region 2) page mode and synchronous mode capabilities defined in "burst read information" bit 0 = page mode host reads permitted (1 = yes, 0 = no) bit 1 = synchronous host reads permitted (1 = yes, 0 = no) bit 2 = synchronous host writes permitted (1 = yes, 0 = no) bits 3-7 = reserved for future use page mode, top parameter 75: 0001h bit 0=1 yes bit 1=0 no bit 2=0 no page mode, bottom parameter n/a n/a 76h 1 features space definitions (reserved for future use) 76: ffffh reserved 77h reserved for future use 77: ffffh reserved rev. 2.44 fum00701 79 page mode, top parameter: the device which supports page mode read operations and contains the parameter blocks at the highest address. page mode, bottom parameter: the device which supports page mode read operations and contains the parameter blocks at the lowest address. rev. 2.44 fum00701 80 7 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-003-cfi-e common flash memory interface specification ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit rev. 2.44 |
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